053ec0508e
The only source of documentation for this device is verilog, so driver is minimalistic. Reviewed by: Dr Jonathan Kimmitt <jrrk2@cam.ac.uk> Approved by: re (kib) Sponsored by: DARPA, AFRL
67 lines
2.7 KiB
C
67 lines
2.7 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _UART_DEV_LOWRISC_H_
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#define _UART_DEV_LOWRISC_H_
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#define UART_DR 0x0000
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#define DR_DATA_S 0
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#define DR_DATA_M 0xff
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#define DR_RX_ERR (1 << 8)
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#define DR_RX_FIFO_EMPTY (1 << 9)
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#define DR_TX_FIFO_FULL (1 << 10)
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#define DR_RX_FIFO_FULL (1 << 11)
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#define UART_INT_STATUS 0x1000
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#define INT_STATUS_ACK 1
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#define UART_BAUD 0x2000 /* write-only */
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#define BAUD_115200 108
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#define UART_STAT_RX 0x2000 /* read-only */
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#define STAT_RX_FIFO_RD_COUNT_S 0
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#define STAT_RX_FIFO_RD_COUNT_M (0xffff << STAT_RX_FIFO_RD_COUNT_S)
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#define STAT_RX_FIFO_WR_COUNT_S 16
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#define STAT_RX_FIFO_WR_COUNT_M (0xffff << STAT_RX_FIFO_WR_COUNT_S)
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#define UART_STAT_TX 0x2004
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#define STAT_TX_FIFO_RD_COUNT_S 0
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#define STAT_TX_FIFO_RD_COUNT_M (0xffff << STAT_TX_FIFO_RD_COUNT_S)
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#define STAT_TX_FIFO_WR_COUNT_S 16
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#define STAT_TX_FIFO_WR_COUNT_M (0xffff << STAT_TX_FIFO_WR_COUNT_S)
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#define GETREG(bas, reg) \
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bus_space_read_2((bas)->bst, (bas)->bsh, (reg))
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#define SETREG(bas, reg, value) \
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bus_space_write_2((bas)->bst, (bas)->bsh, (reg), (value))
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#endif /* _UART_DEV_LOWRISC_H_ */
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