Ian Lepore 61bc42f782 Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around ... TI OMAP controllers which will return the reset-in-progress bit as zero if you read the status register too fast after setting the reset bit. The zero is apparently from a stale snapshot of the internal state presented in the interface register, and leads to a false indication that the reset is complete when it either hasn't started yet or is in-progress. The workaround is to first loop until the bit is seen as asserted, then do the normal loop waiting to see it de-asserted. Submitted by: Michal Meloun <meloun@miracle.cz>		2014-12-20 01:13:13 +00:00
..
sdhci_fdt.c	- Nuke unused sdhci_softc.	2014-08-31 17:56:54 +00:00
sdhci_if.m	- Nuke unused sdhci_softc.	2014-08-31 17:56:54 +00:00
sdhci_pci.c	class, subclass and progif were never used, so don't bother setting	2014-10-13 16:23:51 +00:00
sdhci.c	Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around	2014-12-20 01:13:13 +00:00
sdhci.h	Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around	2014-12-20 01:13:13 +00:00