Neel Natu 69a5a0bfea Sibyte provides a 64-bit read-only counter that counts at half the processor ... frequency. This counter can be accessed coherently from both cores. Use this as the preferred timecounter for the SWARM kernels. The CP0 COUNT register is unusable as the timecounter on SMP platforms because the COUNT registers on different CPUs are not guaranteed to be in sync.		2010-03-20 05:49:06 +00:00
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ata_zbbus.c
files.sibyte	With this commit our friend RMI will now compile. I have	2009-10-30 08:53:11 +00:00
sb_asm.S	Make sure that the registers 'v0' and 'v1' are properly sign-extended	2010-03-20 05:21:14 +00:00
sb_bus_space.h	Various fixes to get the SWARM config working on a big-endian Sibyte CPU.	2010-02-17 06:43:37 +00:00
sb_machdep.c	Sibyte provides a 64-bit read-only counter that counts at half the processor	2010-03-20 05:49:06 +00:00
sb_scd.c	Sibyte provides a 64-bit read-only counter that counts at half the processor	2010-03-20 05:49:06 +00:00
sb_scd.h	Sibyte provides a 64-bit read-only counter that counts at half the processor	2010-03-20 05:49:06 +00:00
sb_zbbus.c	SMP support for the mips port.	2010-02-09 06:24:43 +00:00
sb_zbpci.c	Various fixes to get the SWARM config working on a big-endian Sibyte CPU.	2010-02-17 06:43:37 +00:00