80d0f8c941
the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
432 lines
9.7 KiB
C
432 lines
9.7 KiB
C
/*
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* Copyright (c) 2000 Andrew Gallatin & Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* T2 CBUS to PCI bridge
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <alpha/pci/t2reg.h>
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#include <alpha/pci/t2var.h>
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#include <alpha/pci/pcibus.h>
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#include <alpha/isa/isavar.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include <machine/intrcnt.h>
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#include <machine/cpuconf.h>
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#include <machine/swiz.h>
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#include <machine/sgmap.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa + t2_csr_base)
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vm_offset_t t2_csr_base = 0UL;
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static devclass_t t2_devclass;
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static device_t t2_0; /* XXX only one for now */
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struct t2_softc {
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int junk;
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};
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#define T2_SOFTC(dev) (struct t2_softc*) device_get_softc(dev)
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static alpha_chipset_read_hae_t t2_read_hae;
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static alpha_chipset_write_hae_t t2_write_hae;
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static alpha_chipset_t t2_chipset = {
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t2_read_hae,
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t2_write_hae,
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};
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static u_int32_t t2_hae_mem;
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#define REG1 (1UL << 24)
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static u_int32_t
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t2_set_hae_mem(void *arg, u_int32_t pa)
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{
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int s;
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u_int32_t msb;
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if(pa >= REG1){
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msb = pa & 0xf8000000;
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pa -= msb;
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msb >>= 27; /* t2 puts high bits in the bottom of the register */
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s = splhigh();
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if (msb != t2_hae_mem) {
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t2_hae_mem = msb;
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REGVAL(T2_HAE0_1) = t2_hae_mem;
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alpha_mb();
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t2_hae_mem = REGVAL(T2_HAE0_1);
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}
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splx(s);
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}
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return pa;
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}
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static u_int64_t
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t2_read_hae(void)
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{
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return t2_hae_mem << 27;
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}
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static void
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t2_write_hae(u_int64_t hae)
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{
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u_int32_t pa = hae;
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t2_set_hae_mem(0, pa);
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}
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static int t2_probe(device_t dev);
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static int t2_attach(device_t dev);
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static int t2_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags,
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void *intr, void *arg, void **cookiep);
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static int t2_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie);
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static void
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t2_dispatch_intr(void *frame, unsigned long vector);
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static void
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t2_machine_check(unsigned long mces, struct trapframe *framep,
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unsigned long vector, unsigned long param);
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static device_method_t t2_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, t2_probe),
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DEVMETHOD(device_attach, t2_attach),
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/* Bus interface */
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DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
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DEVMETHOD(bus_release_resource, pci_release_resource),
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DEVMETHOD(bus_activate_resource, pci_activate_resource),
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DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
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DEVMETHOD(bus_setup_intr, t2_setup_intr),
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DEVMETHOD(bus_teardown_intr, t2_teardown_intr),
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{ 0, 0 }
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};
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static driver_t t2_driver = {
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"t2",
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t2_methods,
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sizeof(struct t2_softc),
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};
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#define T2_SGMAP_BASE (8*1024*1024)
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#define T2_SGMAP_SIZE (8*1024*1024)
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static void
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t2_sgmap_invalidate(void)
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{
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u_int64_t val;
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alpha_mb();
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val = REGVAL64(T2_IOCSR);
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val |= T2_IOCSRL_ITLB;
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REGVAL64(T2_IOCSR) = val;
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alpha_mb();
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alpha_mb();
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val = REGVAL64(T2_IOCSR);
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val &= ~T2_IOCSRL_ITLB;
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REGVAL64(T2_IOCSR) = val;
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alpha_mb();
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alpha_mb();
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}
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static void
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t2_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
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{
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u_int64_t *sgtable = arg;
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int index = alpha_btop(ba - T2_SGMAP_BASE);
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if (pa) {
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if (pa > (1L<<32))
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panic("t2_sgmap_map: can't map address 0x%lx", pa);
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sgtable[index] = ((pa >> 13) << 1) | 1;
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} else {
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sgtable[index] = 0;
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}
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alpha_mb();
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t2_sgmap_invalidate();
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}
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static void
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t2_init_sgmap(void)
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{
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void *sgtable;
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/*
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* First setup Window 2 to map 8Mb to 16Mb with an
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* sgmap. Allocate the map aligned to a 32 boundary.
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*
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* bits 31..20 of WBASE represent the pci start address
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* (in units of 1Mb), and bits 11..0 represent the pci
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* end address
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*/
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REGVAL(T2_WBASE2) = T2_WSIZE_8M|T2_WINDOW_ENABLE|T2_WINDOW_SG
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| ((T2_SGMAP_BASE >> 20) << 20)
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| ((T2_SGMAP_BASE + T2_SGMAP_SIZE) >> 20);
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REGVAL(T2_WMASK2) = T2_WMASK_8M;
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alpha_mb();
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sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
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0, (1L<<34),
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32*1024, (1L<<34));
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if (!sgtable)
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panic("t2_init_sgmap: can't allocate page table");
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REGVAL(T2_TBASE2) =
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(pmap_kextract((vm_offset_t) sgtable) >> T2_TBASE_SHIFT);
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chipset.sgmap = sgmap_map_create(T2_SGMAP_BASE,
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T2_SGMAP_BASE + T2_SGMAP_SIZE,
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t2_sgmap_map, sgtable);
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}
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/*
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* Perform basic chipset init/fixup. Called by various early
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* consumers to ensure that the system will work before the
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* bus methods are invoked.
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*
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*/
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void
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t2_init()
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{
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static int initted = 0;
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static struct swiz_space io_space, mem_space;
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if (initted) return;
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initted = 1;
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swiz_init_space(&io_space, KV(T2_PCI_SIO));
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swiz_init_space_hae(&mem_space, KV(T2_PCI_SPARSE),
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t2_set_hae_mem, 0);
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busspace_isa_io = (kobj_t) &io_space;
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busspace_isa_mem = (kobj_t) &mem_space;
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chipset = t2_chipset;
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}
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static int
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t2_probe(device_t dev)
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{
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device_t child;
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if (t2_0)
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return ENXIO;
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t2_0 = dev;
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device_set_desc(dev, "T2 Core Logic chipset");
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pci_init_resources();
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/*
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* initialize the DMA windows
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*/
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REGVAL(T2_WBASE1) = T2_WSIZE_1G|T2_WINDOW_ENABLE|T2_WINDOW_DIRECT|0x7ff;
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REGVAL(T2_WMASK1) = T2_WMASK_1G;
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REGVAL(T2_TBASE1) = 0;
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REGVAL(T2_WBASE2) = 0x0;
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/*
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* enable the PCI "Hole" for ISA devices which use memory in
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* the 512k - 1MB range
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*/
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REGVAL(T2_HBASE) = 1 << 13;
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t2_init_sgmap();
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/* initialize the HAEs */
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REGVAL(T2_HAE0_1) = 0x0;
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alpha_mb();
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REGVAL(T2_HAE0_2) = 0x0;
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alpha_mb();
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REGVAL(T2_HAE0_3) = 0x0;
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alpha_mb();
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child = device_add_child(dev, "pcib", 0);
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device_set_ivars(child, 0);
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return 0;
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}
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static int
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t2_attach(device_t dev)
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{
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t2_init();
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platform.mcheck_handler = t2_machine_check;
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set_iointr(t2_dispatch_intr);
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platform.isa_setup_intr = t2_setup_intr;
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platform.isa_teardown_intr = t2_teardown_intr;
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snprintf(chipset_type, sizeof(chipset_type), "t2");
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bus_generic_attach(dev);
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return 0;
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}
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/*
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* magical mystery table partly obtained from Linux
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* at least some of their values for PCI masks
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* were incorrect, and I've filled in my own extrapolations
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* XXX this needs more testers
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*/
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unsigned long t2_shadow_mask = -1L;
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static const char irq_to_mask[40] = {
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-1, 6, -1, 8, 15, 12, 7, 9, /* ISA 0-7 */
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-1, 16, 17, 18, 3, -1, 21, 22, /* ISA 8-15 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* ?? EISA XXX */
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-1, -1, -1, -1, -1, -1, -1, -1, /* ?? EISA XXX */
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0, 1, 2, 3, 4, 5, 6, 7 /* PCI 0-7 XXX */
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};
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static int
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t2_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags,
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void *intr, void *arg, void **cookiep)
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{
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int error, mask, vector;
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mask = irq_to_mask[irq->r_start];
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vector = 0x800 + (mask << 4);
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error = rman_activate_resource(irq);
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if (error)
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return error;
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error = alpha_setup_intr(vector,
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intr, arg, cookiep,
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&intrcnt[irq->r_start]);
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if (error)
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return error;
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/* Enable interrupt */
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t2_shadow_mask &= ~(1UL << mask);
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if (mask <= 7)
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outb(SLAVE0_ICU, t2_shadow_mask);
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else if (mask <= 15)
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outb(SLAVE1_ICU, t2_shadow_mask >> 8);
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else
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outb(SLAVE2_ICU, t2_shadow_mask >> 16);
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device_printf(child, "interrupting at T2 irq %d\n",
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(int) irq->r_start);
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return 0;
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}
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static int
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t2_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie)
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{
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int mask;
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mask = irq_to_mask[irq->r_start];
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/* Disable interrupt */
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t2_shadow_mask |= (1UL << mask);
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if (mask <= 7)
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outb(SLAVE0_ICU, t2_shadow_mask);
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else if (mask <= 15)
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outb(SLAVE1_ICU, t2_shadow_mask >> 8);
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else
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outb(SLAVE2_ICU, t2_shadow_mask >> 16);
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alpha_teardown_intr(cookie);
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return rman_deactivate_resource(irq);
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}
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static void
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t2_ack_intr(unsigned long vector)
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{
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int mask = (vector - 0x800) >> 4;
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switch (mask) {
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case 0 ... 7:
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outb(SLAVE0_ICU-1, (0xe0 | (mask)));
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outb(MASTER_ICU-1, (0xe0 | 1));
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break;
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case 8 ... 15:
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outb(SLAVE1_ICU-1, (0xe0 | (mask - 8)));
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outb(MASTER_ICU-1, (0xe0 | 3));
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break;
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case 16 ... 24:
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outb(SLAVE2_ICU-1, (0xe0 | (mask - 16)));
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outb(MASTER_ICU-1, (0xe0 | 4));
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break;
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}
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}
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static void
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t2_dispatch_intr(void *frame, unsigned long vector)
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{
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alpha_dispatch_intr(frame, vector);
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t2_ack_intr(vector);
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}
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static void
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t2_machine_check(unsigned long mces, struct trapframe *framep,
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unsigned long vector, unsigned long param)
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{
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int expected;
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expected = mc_expected;
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machine_check(mces, framep, vector, param);
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/* for some reason the alpha_pal_wrmces() doesn't clear all
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pending machine checks & we may take another */
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mc_expected = expected;
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}
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DRIVER_MODULE(t2, root, t2_driver, t2_devclass, 0, 0);
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