af3dc4a7ca
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
318 lines
10 KiB
C
318 lines
10 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2009 Sylvestre Gallon. All rights reserved.
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* Copyright (c) 2010 Greg Ansley. All rights reserved.
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* Copyright (c) 2012 M. Warener Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef AT91SAM9X5REG_H_
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#define AT91SAM9X5REG_H_
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#ifndef AT91SAM9X25_MASTER_CLOCK
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#define AT91SAM9X25_MASTER_CLOCK ((18432000 * 43)/6)
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#endif
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/* Chip Specific limits */
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#define SAM9X25_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */
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#define SAM9X25_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */
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#define SAM9X25_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */
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#define SAM9X25_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */
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#define SAM9X25_PLL_A_MUL_SHIFT 16
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#define SAM9X25_PLL_A_MUL_MASK 0xFF
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#define SAM9X25_PLL_A_DIV_SHIFT 0
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#define SAM9X25_PLL_A_DIV_MASK 0xFF
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#define SAM9X25_PLL_B_MIN_IN_FREQ 2000000 /* 2 Mhz */
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#define SAM9X25_PLL_B_MAX_IN_FREQ 32000000 /* 32 Mhz */
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#define SAM9X25_PLL_B_MIN_OUT_FREQ 30000000 /* 30 Mhz */
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#define SAM9X25_PLL_B_MAX_OUT_FREQ 100000000 /* 100 Mhz */
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#define SAM9X25_PLL_B_MUL_SHIFT 16
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#define SAM9X25_PLL_B_MUL_MASK 0x3F
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#define SAM9X25_PLL_B_DIV_SHIFT 0
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#define SAM9X25_PLL_B_DIV_MASK 0xFF
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/*
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* Memory map, from datasheet :
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* 0x00000000 - 0x0ffffffff : Internal Memories
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* 0x10000000 - 0x1ffffffff : Chip Select 0
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* 0x20000000 - 0x2ffffffff : Chip Select 1 DDR2/LPDDR/SDR/LPSDR
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* 0x30000000 - 0x3ffffffff : Chip Select 2
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* 0x40000000 - 0x4ffffffff : Chip Select 3 NAND Flash
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* 0x50000000 - 0x5ffffffff : Chip Select 4
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* 0x60000000 - 0x6ffffffff : Chip Select 5
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* 0x70000000 - 0xeffffffff : Undefined (Abort)
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* 0xf0000000 - 0xfffffffff : Peripherals
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*/
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#define AT91_CHIPSELECT_0 0x10000000
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#define AT91_CHIPSELECT_1 0x20000000
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#define AT91_CHIPSELECT_2 0x30000000
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#define AT91_CHIPSELECT_3 0x40000000
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#define AT91_CHIPSELECT_4 0x50000000
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#define AT91_CHIPSELECT_5 0x60000000
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#define AT91SAM9X25_EMAC_SIZE 0x4000
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#define AT91SAM9X25_EMAC0_BASE 0x802c000
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#define AT91SAM9X25_EMAC0_SIZE AT91SAM9X25_EMAC_SIZE
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#define AT91SAM9X25_EMAC1_BASE 0x8030000
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#define AT91SAM9X25_EMAC1_SIZE AT91SAM9X25_EMAC_SIZE
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#define AT91SAM9X25_RSTC_BASE 0xffffe00
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#define AT91SAM9X25_RSTC_SIZE 0x10
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/* USART*/
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#define AT91SAM9X25_USART_SIZE 0x4000
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#define AT91SAM9X25_USART0_BASE 0x801c000
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#define AT91SAM9X25_USART0_PDC 0x801c100
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#define AT91SAM9X25_USART0_SIZE AT91SAM9X25_USART_SIZE
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#define AT91SAM9X25_USART1_BASE 0x8020000
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#define AT91SAM9X25_USART1_PDC 0x8020100
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#define AT91SAM9X25_USART1_SIZE AT91SAM9X25_USART_SIZE
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#define AT91SAM9X25_USART2_BASE 0x8024000
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#define AT91SAM9X25_USART2_PDC 0x8024100
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#define AT91SAM9X25_USART2_SIZE AT91SAM9X25_USART_SIZE
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#define AT91SAM9X25_USART3_BASE 0x8028000
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#define AT91SAM9X25_USART3_PDC 0x8028100
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#define AT91SAM9X25_USART3_SIZE AT91SAM9X25_USART_SIZE
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/*TC*/
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#define AT91SAM9X25_TC0_BASE 0x8008000
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#define AT91SAM9X25_TC0_SIZE 0x4000
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#define AT91SAM9X25_TC0C0_BASE 0x8008000
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#define AT91SAM9X25_TC0C1_BASE 0x8008040
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#define AT91SAM9X25_TC0C2_BASE 0x8008080
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#define AT91SAM9X25_TC1_BASE 0x800c000
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#define AT91SAM9X25_TC1_SIZE 0x4000
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/*SPI*/
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#define AT91SAM9X25_SPI0_BASE 0x0000000
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#define AT91SAM9X25_SPI0_SIZE 0x4000
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#define AT91SAM9X25_SPI1_BASE 0x0004000
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#define AT91SAM9X25_SPI1_SIZE 0x4000
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/* System Registers */
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#define AT91SAM9X25_SYS_BASE 0xffff000
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#define AT91SAM9X25_SYS_SIZE 0x1000
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#define AT91SAM9X25_MATRIX_BASE 0xfffde00
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#define AT91SAM9X25_MATRIX_SIZE 0x200
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#define AT91SAM9X25_DBGU_BASE 0xffff200
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#define AT91SAM9X25_DBGU_SIZE 0x200
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/*
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* PIO
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*/
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#define AT91SAM9X25_PIOA_BASE 0xffff400
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#define AT91SAM9X25_PIOA_SIZE 0x200
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#define AT91SAM9X25_PIOB_BASE 0xffff600
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#define AT91SAM9X25_PIOB_SIZE 0x200
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#define AT91SAM9X25_PIOC_BASE 0xffff800
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#define AT91SAM9X25_PIOC_SIZE 0x200
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#define AT91SAM9X25_PIOD_BASE 0xffffa00
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#define AT91SAM9X25_PIOD_SIZE 0x200
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#define AT91RM92_PMC_BASE 0xffffc00
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#define AT91RM92_PMC_SIZE 0x100
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/* IRQs :
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* 0: AIC
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* 1: System peripheral (System timer, RTC, DBGU)
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* 2: PIO Controller A,B
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* 3: PIO Controller C,D
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* 4: SMD Soft Modem
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* 5: USART 0
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* 6: USART 1
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* 7: USART 2
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* 8: USART 3
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* 9: Two-wire interface
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* 10: Two-wire interface
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* 11: Two-wire interface
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* 12: HSMCI Interface
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* 13: SPI 0
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* 14: SPI 1
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* 15: UART0
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* 16: UART1
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* 17: Timer Counter 0,1
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* 18: PWM
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* 19: ADC
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* 20: DMAC 0
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* 21: DMAC 1
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* 22: UHPHS - USB Host controller
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* 23: UDPHS - USB Device Controller
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* 24: EMAC0
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* 25: LCD controller or Image Sensor Interface
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* 26: HSMCI1
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* 27: EMAC1
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* 28: SSC
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* 29: CAN0
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* 30: CAN1
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* 31: AIC IRQ0
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*/
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#define AT91SAM9X25_IRQ_AIC 0
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#define AT91SAM9X25_IRQ_SYSTEM 1
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#define AT91SAM9X25_IRQ_PIOAB 2
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#define AT91SAM9X25_IRQ_PIOCD 3
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#define AT91SAM9X25_IRQ_SMD 4
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#define AT91SAM9X25_IRQ_USART0 5
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#define AT91SAM9X25_IRQ_USART1 6
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#define AT91SAM9X25_IRQ_USART2 7
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#define AT91SAM9X25_IRQ_USART3 8
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#define AT91SAM9X25_IRQ_TWI0 9
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#define AT91SAM9X25_IRQ_TWI1 10
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#define AT91SAM9X25_IRQ_TWI2 11
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#define AT91SAM9X25_IRQ_HSMCI0 12
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#define AT91SAM9X25_IRQ_SPI0 13
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#define AT91SAM9X25_IRQ_SPI1 14
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#define AT91SAM9X25_IRQ_UART0 15
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#define AT91SAM9X25_IRQ_UART1 16
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#define AT91SAM9X25_IRQ_TC01 17
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#define AT91SAM9X25_IRQ_PWM 18
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#define AT91SAM9X25_IRQ_ADC 19
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#define AT91SAM9X25_IRQ_DMAC0 20
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#define AT91SAM9X25_IRQ_DMAC1 21
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#define AT91SAM9X25_IRQ_UHPHS 22
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#define AT91SAM9X25_IRQ_UDPHS 23
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#define AT91SAM9X25_IRQ_EMAC0 24
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#define AT91SAM9X25_IRQ_HSMCI1 26
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#define AT91SAM9X25_IRQ_EMAC1 27
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#define AT91SAM9X25_IRQ_SSC 28
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#define AT91SAM9X25_IRQ_CAN0 29
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#define AT91SAM9X25_IRQ_CAN1 30
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#define AT91SAM9X25_IRQ_AICBASE 31
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/* Alias */
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#define AT91SAM9X25_IRQ_DBGU AT91SAM9X25_IRQ_SYSTEM
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#define AT91SAM9X25_IRQ_PMC AT91SAM9X25_IRQ_SYSTEM
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#define AT91SAM9X25_IRQ_WDT AT91SAM9X25_IRQ_SYSTEM
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#define AT91SAM9X25_IRQ_PIT AT91SAM9X25_IRQ_SYSTEM
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#define AT91SAM9X25_IRQ_RSTC AT91SAM9X25_IRQ_SYSTEM
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#define AT91SAM9X25_IRQ_OHCI AT91SAM9X25_IRQ_UHPHS
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#define AT91SAM9X25_IRQ_EHCI AT91SAM9X25_IRQ_UHPHS
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#define AT91SAM9X25_IRQ_PIOA AT91SAM9X25_IRQ_PIOAB
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#define AT91SAM9X25_IRQ_PIOB AT91SAM9X25_IRQ_PIOAB
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#define AT91SAM9X25_IRQ_PIOC AT91SAM9X25_IRQ_PIOCD
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#define AT91SAM9X25_IRQ_PIOD AT91SAM9X25_IRQ_PIOCD
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#define AT91SAM9X25_IRQ_NAND (-1)
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#define AT91SAM9X25_AIC_BASE 0xffff000
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#define AT91SAM9X25_AIC_SIZE 0x200
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/* Timer */
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#define AT91SAM9X25_WDT_BASE 0xffffd40
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#define AT91SAM9X25_WDT_SIZE 0x10
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#define AT91SAM9X25_PIT_BASE 0xffffd30
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#define AT91SAM9X25_PIT_SIZE 0x10
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#define AT91SAM9X25_SMC_BASE 0xfffea00
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#define AT91SAM9X25_SMC_SIZE 0x200
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#define AT91SAM9X25_PMC_BASE 0xffffc00
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#define AT91SAM9X25_PMC_SIZE 0x100
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#define AT91SAM9X25_UDPHS_BASE 0x803c000
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#define AT91SAM9X25_UDPHS_SIZE 0x4000
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#define AT91SAM9X25_HSMCI_SIZE 0x4000
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#define AT91SAM9X25_HSMCI0_BASE 0x0008000
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#define AT91SAM9X25_HSMCI0_SIZE AT91SAM9X25_HSMCI_SIZE
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#define AT91SAM9X25_HSMCI1_BASE 0x000c000
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#define AT91SAM9X25_HSMCI1_SIZE AT91SAM9X25_HSMCI_SIZE
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#define AT91SAM9X25_TWI_SIZE 0x4000
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#define AT91SAM9X25_TWI0_BASE 0xffaC000
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#define AT91SAM9X25_TWI0_SIZE AT91SAM9X25_TWI_SIZE
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#define AT91SAM9X25_TWI1_BASE 0xffaC000
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#define AT91SAM9X25_TWI1_SIZE AT91SAM9X25_TWI_SIZE
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#define AT91SAM9X25_TWI2_BASE 0xffaC000
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#define AT91SAM9X25_TWI2_SIZE AT91SAM9X25_TWI_SIZE
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/* XXX Needs to be carfully coordinated with
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* other * soc's so phyical and vm address
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* mapping are unique. XXX
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*/
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#define AT91SAM9X25_OHCI_BASE 0xdfc00000 /* SAME as 9c40 */
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#define AT91SAM9X25_OHCI_PA_BASE 0x00600000
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#define AT91SAM9X25_OHCI_SIZE 0x00100000
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#define AT91SAM9X25_EHCI_BASE 0xdfd00000
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#define AT91SAM9X25_EHCI_PA_BASE 0x00700000
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#define AT91SAM9X25_EHCI_SIZE 0x00100000
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#define AT91SAM9X25_NAND_BASE 0xe0000000
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#define AT91SAM9X25_NAND_PA_BASE 0x40000000
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#define AT91SAM9X25_NAND_SIZE 0x10000000
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/* SDRAMC */
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#define AT91SAM9X25_SDRAMC_BASE 0xfffea00 /* SAME as SMC? */
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#define AT91SAM9X25_SDRAMC_MR 0x00
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#define AT91SAM9X25_SDRAMC_MR_MODE_NORMAL 0
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#define AT91SAM9X25_SDRAMC_MR_MODE_NOP 1
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#define AT91SAM9X25_SDRAMC_MR_MODE_PRECHARGE 2
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#define AT91SAM9X25_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
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#define AT91SAM9X25_SDRAMC_MR_MODE_REFRESH 4
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#define AT91SAM9X25_SDRAMC_TR 0x04
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#define AT91SAM9X25_SDRAMC_CR 0x08
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#define AT91SAM9X25_SDRAMC_CR_NC_8 0x0
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#define AT91SAM9X25_SDRAMC_CR_NC_9 0x1
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#define AT91SAM9X25_SDRAMC_CR_NC_10 0x2
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#define AT91SAM9X25_SDRAMC_CR_NC_11 0x3
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#define AT91SAM9X25_SDRAMC_CR_NC_MASK 0x00000003
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#define AT91SAM9X25_SDRAMC_CR_NR_11 0x0
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#define AT91SAM9X25_SDRAMC_CR_NR_12 0x4
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#define AT91SAM9X25_SDRAMC_CR_NR_13 0x8
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#define AT91SAM9X25_SDRAMC_CR_NR_RES 0xc
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#define AT91SAM9X25_SDRAMC_CR_NR_MASK 0x0000000c
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#define AT91SAM9X25_SDRAMC_CR_NB_2 0x00
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#define AT91SAM9X25_SDRAMC_CR_NB_4 0x10
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#define AT91SAM9X25_SDRAMC_CR_DBW_16 0x80
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#define AT91SAM9X25_SDRAMC_CR_NB_MASK 0x00000010
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#define AT91SAM9X25_SDRAMC_CR_NCAS_MASK 0x00000060
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#define AT91SAM9X25_SDRAMC_CR_TWR_MASK 0x00000780
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#define AT91SAM9X25_SDRAMC_CR_TRC_MASK 0x00007800
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#define AT91SAM9X25_SDRAMC_CR_TRP_MASK 0x00078000
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#define AT91SAM9X25_SDRAMC_CR_TRCD_MASK 0x00780000
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#define AT91SAM9X25_SDRAMC_CR_TRAS_MASK 0x07800000
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#define AT91SAM9X25_SDRAMC_CR_TXSR_MASK 0x78000000
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#define AT91SAM9X25_SDRAMC_HSR 0x0c
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#define AT91SAM9X25_SDRAMC_LPR 0x10
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#define AT91SAM9X25_SDRAMC_IER 0x14
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#define AT91SAM9X25_SDRAMC_IDR 0x18
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#define AT91SAM9X25_SDRAMC_IMR 0x1c
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#define AT91SAM9X25_SDRAMC_ISR 0x20
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#define AT91SAM9X25_SDRAMC_MDR 0x24
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#endif /* AT91SAM9X5REG_H_*/
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