freebsd-dev/sys/gnu/dts/mips/TEW-692GR.dts
Stanislav Galabov 179f14534e Import LEDE dts files for Ralink/Mediatek
This is an import of the reworked LEDE dts files. Besides other things
they make it easier for us to reuse.

The only diffs left are for the following SoCs:
MT7620A (fbsd-mt7620a.dtsi)
MT7621 (fbsd-mt7621.dtsi)
MT7628 (fbsd-mt7628an.dtsi)
RT3883 (fbsd-rt3883.dtsi)

So we include the fbsd-*.dtsi files at the end of the original LEDE dtsi
files, using '#include "fbsd-xxxx.dtsi"'.
For example, for MT7621, the LEDE dtsi file is mt7621.dtsi. At the end of
it we add:
#include "fbsd-mt7621.dtsi"

Approved by:	adrian (mentor)
Obtained from:	LEDE project
Sponsored by:	Smartcom - Bulgaria AD
Differential Revision:	https://reviews.freebsd.org/D6394
2016-05-17 06:42:24 +00:00

127 lines
1.7 KiB
Plaintext

/dts-v1/;
#include "rt3883.dtsi"
/ {
compatible = "TEW-692GR", "ralink,rt3883-soc";
model = "TRENDnet TEW-692GR";
nor-flash@1c000000 {
compatible = "cfi-flash";
reg = <0x1c000000 0x800000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x0030000>;
label = "u-boot";
read-only;
};
partition@30000 {
reg = <0x00030000 0x00010000>;
label = "u-boot-env";
read-only;
};
factory: partition@40000 {
reg = <0x00040000 0x00010000>;
label = "factory";
read-only;
};
partition@50000 {
reg = <0x00050000 0x007b0000>;
label = "firmware";
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
reset {
label = "reset";
gpios = <&gpio0 10 1>;
linux,code = <0x198>;
};
wps {
label = "wps";
gpios = <&gpio1 2 1>;
linux,code = <0x211>;
};
};
gpio-leds {
compatible = "gpio-leds";
wps {
label = "tew-692gr:orange:wps";
gpios = <&gpio0 9 1>;
};
wps2 {
label = "tew-692gr:green:wps";
gpios = <&gpio1 4 1>;
};
};
};
&gpio1 {
status = "okay";
};
&pinctrl {
state_default: pinctrl0 {
gpio {
ralink,group = "spi", "i2c", "jtag", "uartf";
ralink,function = "gpio";
};
};
};
&ethernet {
status = "okay";
mtd-mac-address = <&factory 0x28>;
port@0 {
phy-handle = <&phy0>;
phy-mode = "rgmii";
};
mdio-bus {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&pci {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pci_pins>;
pci_pins: pci {
pci {
ralink,group = "pci";
ralink,function = "pci-fnc";
};
};
host-bridge {
pci-bridge@1 {
status = "okay";
};
};
};
&wmac {
ralink,5ghz = <0>;
};