1fa7f10bac
domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
40 lines
746 B
Makefile
40 lines
746 B
Makefile
#
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# $FreeBSD$
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#
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.PATH: ${.CURDIR}/../../dev/hwpmc
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KMOD= hwpmc
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SRCS= hwpmc_mod.c hwpmc_logging.c vnode_if.h
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.if ${MACHINE_ARCH} == "amd64"
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SRCS+= hwpmc_amd.c hwpmc_core.c hwpmc_intel.c hwpmc_piv.c hwpmc_tsc.c
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SRCS+= hwpmc_x86.c hwpmc_uncore.c
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SRCS+= device_if.h bus_if.h
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.endif
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.if ${MACHINE_ARCH} == "arm"
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SRCS+= hwpmc_arm.c
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.endif
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.if ${MACHINE_ARCH} == "i386"
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SRCS+= hwpmc_amd.c hwpmc_core.c hwpmc_intel.c hwpmc_piv.c hwpmc_ppro.c
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SRCS+= hwpmc_pentium.c hwpmc_tsc.c hwpmc_x86.c hwpmc_uncore.c
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SRCS+= device_if.h bus_if.h
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.endif
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.if ${MACHINE_ARCH} == "ia64"
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SRCS+= hwpmc_ia64.c
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.endif
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.if ${MACHINE_ARCH} == "powerpc"
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SRCS+= hwpmc_powerpc.c
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.endif
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.if ${MACHINE_ARCH} == "sparc64"
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SRCS+= hwpmc_sparc64.c
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.endif
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.include <bsd.kmod.mk>
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