Without disabling interrupts it's possible for another thread to preempt and update the registers post-read (tlb1_read_entry) or pre-write (tlb1_write_entry), and confuse the kernel with mixed register states. MFC after: 2 weeks |
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.. | ||
booke_machdep.c | ||
locore.S | ||
machdep_e500.c | ||
machdep_ppc4xx.c | ||
mp_cpudep.c | ||
platform_bare.c | ||
pmap.c | ||
spe.c | ||
trap_subr.S |