Justin Hibbits 3d1357108a Disable interrupts when updating the TLB ... Without disabling interrupts it's possible for another thread to preempt and update the registers post-read (tlb1_read_entry) or pre-write (tlb1_write_entry), and confuse the kernel with mixed register states. MFC after: 2 weeks		2017-06-27 01:57:22 +00:00
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booke_machdep.c	Introduce 64-bit PowerPC Book-E support	2017-03-17 21:40:14 +00:00
locore.S	Introduce 64-bit PowerPC Book-E support	2017-03-17 21:40:14 +00:00
machdep_e500.c	Add platform support for QorIQ SoCs.	2015-12-30 03:43:25 +00:00
machdep_ppc4xx.c	Remove booke_enable_l3_cache declaration and remaining definition.	2016-07-17 19:24:28 +00:00
mp_cpudep.c	Introduce 64-bit PowerPC Book-E support	2017-03-17 21:40:14 +00:00
platform_bare.c
pmap.c	Disable interrupts when updating the TLB	2017-06-27 01:57:22 +00:00
spe.c	Create a new MACHINE_ARCH for Freescale PowerPC e500v2	2016-10-22 01:57:15 +00:00
trap_subr.S	Fix stack tracing in dtrace for powerpc	2017-05-11 00:23:51 +00:00