414 lines
14 KiB
C
414 lines
14 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2016 Anish Gupta (anish@freebsd.org)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _AMDVI_PRIV_H_
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#define _AMDVI_PRIV_H_
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#include <contrib/dev/acpica/include/acpi.h>
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#define BIT(n) (1ULL << (n))
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/* Return value of bits[n:m] where n and (n >= ) m are bit positions. */
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#define REG_BITS(x, n, m) (((x) >> (m)) & \
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((1 << (((n) - (m)) + 1)) - 1))
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/*
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* IOMMU PCI capability.
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*/
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#define AMDVI_PCI_CAP_IOTLB BIT(0) /* IOTLB is supported. */
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#define AMDVI_PCI_CAP_HT BIT(1) /* HyperTransport tunnel support. */
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#define AMDVI_PCI_CAP_NPCACHE BIT(2) /* Not present page cached. */
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#define AMDVI_PCI_CAP_EFR BIT(3) /* Extended features. */
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#define AMDVI_PCI_CAP_EXT BIT(4) /* Miscellaneous information reg. */
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/*
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* IOMMU extended features.
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*/
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#define AMDVI_EX_FEA_PREFSUP BIT(0) /* Prefetch command support. */
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#define AMDVI_EX_FEA_PPRSUP BIT(1) /* PPR support */
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#define AMDVI_EX_FEA_XTSUP BIT(2) /* Reserved */
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#define AMDVI_EX_FEA_NXSUP BIT(3) /* No-execute. */
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#define AMDVI_EX_FEA_GTSUP BIT(4) /* Guest translation support. */
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#define AMDVI_EX_FEA_EFRW BIT(5) /* Reserved */
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#define AMDVI_EX_FEA_IASUP BIT(6) /* Invalidate all command supp. */
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#define AMDVI_EX_FEA_GASUP BIT(7) /* Guest APIC or AVIC support. */
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#define AMDVI_EX_FEA_HESUP BIT(8) /* Hardware Error. */
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#define AMDVI_EX_FEA_PCSUP BIT(9) /* Performance counters support. */
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/* XXX: add more EFER bits. */
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/*
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* Device table entry or DTE
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* NOTE: Must be 256-bits/32 bytes aligned.
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*/
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struct amdvi_dte {
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uint32_t dt_valid:1; /* Device Table valid. */
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uint32_t pt_valid:1; /* Page translation valid. */
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uint16_t :7; /* Reserved[8:2] */
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uint8_t pt_level:3; /* Paging level, 0 to disable. */
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uint64_t pt_base:40; /* Page table root pointer. */
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uint8_t :3; /* Reserved[54:52] */
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uint8_t gv_valid:1; /* Revision 2, GVA to SPA. */
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uint8_t gv_level:2; /* Revision 2, GLX level. */
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uint8_t gv_cr3_lsb:3; /* Revision 2, GCR3[14:12] */
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uint8_t read_allow:1; /* I/O read enabled. */
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uint8_t write_allow:1; /* I/O write enabled. */
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uint8_t :1; /* Reserved[63] */
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uint16_t domain_id:16; /* Domain ID */
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uint16_t gv_cr3_lsb2:16; /* Revision 2, GCR3[30:15] */
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uint8_t iotlb_enable:1; /* Device support IOTLB */
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uint8_t sup_second_io_fault:1; /* Suppress subsequent I/O faults. */
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uint8_t sup_all_io_fault:1; /* Suppress all I/O page faults. */
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uint8_t IOctl:2; /* Port I/O control. */
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uint8_t iotlb_cache_disable:1; /* IOTLB cache hints. */
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uint8_t snoop_disable:1; /* Snoop disable. */
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uint8_t allow_ex:1; /* Allow exclusion. */
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uint8_t sysmgmt:2; /* System management message.*/
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uint8_t :1; /* Reserved[106] */
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uint32_t gv_cr3_msb:21; /* Revision 2, GCR3[51:31] */
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uint8_t intmap_valid:1; /* Interrupt map valid. */
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uint8_t intmap_len:4; /* Interrupt map table length. */
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uint8_t intmap_ign:1; /* Ignore unmapped interrupts. */
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uint64_t intmap_base:46; /* IntMap base. */
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uint8_t :4; /* Reserved[183:180] */
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uint8_t init_pass:1; /* INIT pass through or PT */
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uint8_t extintr_pass:1; /* External Interrupt PT */
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uint8_t nmi_pass:1; /* NMI PT */
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uint8_t :1; /* Reserved[187] */
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uint8_t intr_ctrl:2; /* Interrupt control */
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uint8_t lint0_pass:1; /* LINT0 PT */
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uint8_t lint1_pass:1; /* LINT1 PT */
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uint64_t :64; /* Reserved[255:192] */
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} __attribute__((__packed__));
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CTASSERT(sizeof(struct amdvi_dte) == 32);
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/*
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* IOMMU command entry.
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*/
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struct amdvi_cmd {
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uint32_t word0;
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uint32_t word1:28;
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uint8_t opcode:4;
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uint64_t addr;
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} __attribute__((__packed__));
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/* Command opcodes. */
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#define AMDVI_CMP_WAIT_OPCODE 0x1 /* Completion wait. */
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#define AMDVI_INVD_DTE_OPCODE 0x2 /* Invalidate device table entry. */
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#define AMDVI_INVD_PAGE_OPCODE 0x3 /* Invalidate pages. */
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#define AMDVI_INVD_IOTLB_OPCODE 0x4 /* Invalidate IOTLB pages. */
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#define AMDVI_INVD_INTR_OPCODE 0x5 /* Invalidate Interrupt table. */
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#define AMDVI_PREFETCH_PAGES_OPCODE 0x6 /* Prefetch IOMMU pages. */
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#define AMDVI_COMP_PPR_OPCODE 0x7 /* Complete PPR request. */
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#define AMDVI_INV_ALL_OPCODE 0x8 /* Invalidate all. */
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/* Completion wait attributes. */
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#define AMDVI_CMP_WAIT_STORE BIT(0) /* Write back data. */
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#define AMDVI_CMP_WAIT_INTR BIT(1) /* Completion wait interrupt. */
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#define AMDVI_CMP_WAIT_FLUSH BIT(2) /* Flush queue. */
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/* Invalidate page. */
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#define AMDVI_INVD_PAGE_S BIT(0) /* Invalidation size. */
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#define AMDVI_INVD_PAGE_PDE BIT(1) /* Invalidate PDE. */
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#define AMDVI_INVD_PAGE_GN_GVA BIT(2) /* GPA or GVA. */
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#define AMDVI_INVD_PAGE_ALL_ADDR (0x7FFFFFFFFFFFFULL << 12)
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/* Invalidate IOTLB. */
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#define AMDVI_INVD_IOTLB_S BIT(0) /* Invalidation size 4k or addr */
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#define AMDVI_INVD_IOTLB_GN_GVA BIT(2) /* GPA or GVA. */
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#define AMDVI_INVD_IOTLB_ALL_ADDR (0x7FFFFFFFFFFFFULL << 12)
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/* XXX: add more command entries. */
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/*
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* IOMMU event entry.
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*/
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struct amdvi_event {
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uint16_t devid;
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uint16_t pasid_hi;
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uint16_t pasid_domid; /* PASID low or DomainID */
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uint16_t flag:12;
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uint8_t opcode:4;
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uint64_t addr;
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} __attribute__((__packed__));
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CTASSERT(sizeof(struct amdvi_event) == 16);
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/* Various event types. */
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#define AMDVI_EVENT_INVALID_DTE 0x1
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#define AMDVI_EVENT_PFAULT 0x2
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#define AMDVI_EVENT_DTE_HW_ERROR 0x3
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#define AMDVI_EVENT_PAGE_HW_ERROR 0x4
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#define AMDVI_EVENT_ILLEGAL_CMD 0x5
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#define AMDVI_EVENT_CMD_HW_ERROR 0x6
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#define AMDVI_EVENT_IOTLB_TIMEOUT 0x7
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#define AMDVI_EVENT_INVALID_DTE_REQ 0x8
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#define AMDVI_EVENT_INVALID_PPR_REQ 0x9
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#define AMDVI_EVENT_COUNTER_ZERO 0xA
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#define AMDVI_EVENT_FLAG_MASK 0x1FF /* Mask for event flags. */
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#define AMDVI_EVENT_FLAG_TYPE(x) (((x) >> 9) & 0x3)
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/*
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* IOMMU control block.
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*/
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struct amdvi_ctrl {
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struct {
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uint16_t size:9;
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uint16_t :3;
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uint64_t base:40; /* Devtable register base. */
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uint16_t :12;
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} dte;
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struct {
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uint16_t :12;
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uint64_t base:40;
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uint8_t :4;
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uint8_t len:4;
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uint8_t :4;
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} cmd;
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struct {
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uint16_t :12;
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uint64_t base:40;
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uint8_t :4;
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uint8_t len:4;
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uint8_t :4;
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} event;
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uint16_t control :13;
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uint64_t :51;
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struct {
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uint8_t enable:1;
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uint8_t allow:1;
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uint16_t :10;
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uint64_t base:40;
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uint16_t :12;
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uint16_t :12;
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uint64_t limit:40;
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uint16_t :12;
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} excl;
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/*
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* Revision 2 only.
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*/
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uint64_t ex_feature;
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struct {
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uint16_t :12;
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uint64_t base:40;
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uint8_t :4;
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uint8_t len:4;
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uint8_t :4;
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} ppr;
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uint64_t first_event;
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uint64_t second_event;
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uint64_t event_status;
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/* Revision 2 only, end. */
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uint8_t pad1[0x1FA8]; /* Padding. */
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uint32_t cmd_head:19;
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uint64_t :45;
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uint32_t cmd_tail:19;
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uint64_t :45;
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uint32_t evt_head:19;
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uint64_t :45;
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uint32_t evt_tail:19;
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uint64_t :45;
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uint32_t status:19;
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uint64_t :45;
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uint64_t pad2;
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uint8_t :4;
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uint16_t ppr_head:15;
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uint64_t :45;
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uint8_t :4;
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uint16_t ppr_tail:15;
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uint64_t :45;
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uint8_t pad3[0x1FC0]; /* Padding. */
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/* XXX: More for rev2. */
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} __attribute__((__packed__));
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CTASSERT(offsetof(struct amdvi_ctrl, pad1)== 0x58);
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CTASSERT(offsetof(struct amdvi_ctrl, pad2)== 0x2028);
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CTASSERT(offsetof(struct amdvi_ctrl, pad3)== 0x2040);
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#define AMDVI_MMIO_V1_SIZE (4 * PAGE_SIZE) /* v1 size */
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/*
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* AMF IOMMU v2 size including event counters
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*/
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#define AMDVI_MMIO_V2_SIZE (8 * PAGE_SIZE)
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CTASSERT(sizeof(struct amdvi_ctrl) == 0x4000);
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CTASSERT(sizeof(struct amdvi_ctrl) == AMDVI_MMIO_V1_SIZE);
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/* IVHD flag */
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#define IVHD_FLAG_HTT BIT(0) /* Hypertransport Tunnel. */
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#define IVHD_FLAG_PPW BIT(1) /* Pass posted write. */
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#define IVHD_FLAG_RPPW BIT(2) /* Response pass posted write. */
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#define IVHD_FLAG_ISOC BIT(3) /* Isoc support. */
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#define IVHD_FLAG_IOTLB BIT(4) /* IOTLB support. */
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#define IVHD_FLAG_COH BIT(5) /* Coherent control, default 1 */
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#define IVHD_FLAG_PFS BIT(6) /* Prefetch IOMMU pages. */
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#define IVHD_FLAG_PPRS BIT(7) /* Peripheral page support. */
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/* IVHD device entry data setting. */
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#define IVHD_DEV_LINT0_PASS BIT(6) /* LINT0 interrupts. */
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#define IVHD_DEV_LINT1_PASS BIT(7) /* LINT1 interrupts. */
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/* Bit[5:4] for System Mgmt. Bit3 is reserved. */
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#define IVHD_DEV_INIT_PASS BIT(0) /* INIT */
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#define IVHD_DEV_EXTINTR_PASS BIT(1) /* ExtInt */
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#define IVHD_DEV_NMI_PASS BIT(2) /* NMI */
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/* IVHD 8-byte extended data settings. */
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#define IVHD_DEV_EXT_ATS_DISABLE BIT(31) /* Disable ATS */
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/* IOMMU control register. */
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#define AMDVI_CTRL_EN BIT(0) /* IOMMU enable. */
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#define AMDVI_CTRL_HTT BIT(1) /* Hypertransport tunnel enable. */
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#define AMDVI_CTRL_ELOG BIT(2) /* Event log enable. */
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#define AMDVI_CTRL_ELOGINT BIT(3) /* Event log interrupt. */
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#define AMDVI_CTRL_COMINT BIT(4) /* Completion wait interrupt. */
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#define AMDVI_CTRL_PPW BIT(8)
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#define AMDVI_CTRL_RPPW BIT(9)
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#define AMDVI_CTRL_COH BIT(10)
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#define AMDVI_CTRL_ISOC BIT(11)
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#define AMDVI_CTRL_CMD BIT(12) /* Command buffer enable. */
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#define AMDVI_CTRL_PPRLOG BIT(13)
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#define AMDVI_CTRL_PPRINT BIT(14)
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#define AMDVI_CTRL_PPREN BIT(15)
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#define AMDVI_CTRL_GTE BIT(16) /* Guest translation enable. */
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#define AMDVI_CTRL_GAE BIT(17) /* Guest APIC enable. */
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/* Invalidation timeout. */
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#define AMDVI_CTRL_INV_NO_TO 0 /* No timeout. */
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#define AMDVI_CTRL_INV_TO_1ms 1 /* 1 ms */
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#define AMDVI_CTRL_INV_TO_10ms 2 /* 10 ms */
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#define AMDVI_CTRL_INV_TO_100ms 3 /* 100 ms */
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#define AMDVI_CTRL_INV_TO_1S 4 /* 1 second */
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#define AMDVI_CTRL_INV_TO_10S 5 /* 10 second */
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#define AMDVI_CTRL_INV_TO_100S 6 /* 100 second */
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/*
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* Max number of PCI devices.
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* 256 bus x 32 slot/devices x 8 functions.
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*/
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#define PCI_NUM_DEV_MAX 0x10000
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/* Maximum number of domains supported by IOMMU. */
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#define AMDVI_MAX_DOMAIN (BIT(16) - 1)
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/*
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* IOMMU Page Table attributes.
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*/
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#define AMDVI_PT_PRESENT BIT(0)
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#define AMDVI_PT_COHERENT BIT(60)
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#define AMDVI_PT_READ BIT(61)
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#define AMDVI_PT_WRITE BIT(62)
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#define AMDVI_PT_RW (AMDVI_PT_READ | AMDVI_PT_WRITE)
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#define AMDVI_PT_MASK 0xFFFFFFFFFF000UL /* Only [51:12] for PA */
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#define AMDVI_PD_LEVEL_SHIFT 9
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#define AMDVI_PD_SUPER(x) (((x) >> AMDVI_PD_LEVEL_SHIFT) == 7)
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/*
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* IOMMU Status, offset 0x2020
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*/
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#define AMDVI_STATUS_EV_OF BIT(0) /* Event overflow. */
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#define AMDVI_STATUS_EV_INTR BIT(1) /* Event interrupt. */
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/* Completion wait command completed. */
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#define AMDVI_STATUS_CMP BIT(2)
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#define IVRS_CTRL_RID 1 /* MMIO RID */
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/* ACPI IVHD */
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struct ivhd_dev_cfg {
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uint32_t start_id;
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uint32_t end_id;
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uint8_t data; /* Device configuration. */
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bool enable_ats; /* ATS enabled for the device. */
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int ats_qlen; /* ATS invalidation queue depth. */
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};
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struct amdvi_domain {
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uint64_t *ptp; /* Highest level page table */
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int ptp_level; /* Level of page tables */
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u_int id; /* Domain id */
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SLIST_ENTRY (amdvi_domain) next;
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};
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/*
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* Different type of IVHD.
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* XXX: Use AcpiIvrsType once new IVHD types are available.
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*/
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enum IvrsType
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{
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IVRS_TYPE_HARDWARE_LEGACY = ACPI_IVRS_TYPE_HARDWARE1,
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/* Legacy without EFRi support. */
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IVRS_TYPE_HARDWARE_EFR = ACPI_IVRS_TYPE_HARDWARE2,
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/* With EFR support. */
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IVRS_TYPE_HARDWARE_MIXED = 0x40, /* Mixed with EFR support. */
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};
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/*
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* AMD IOMMU softc.
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*/
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struct amdvi_softc {
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struct amdvi_ctrl *ctrl; /* Control area. */
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device_t dev; /* IOMMU device. */
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enum IvrsType ivhd_type; /* IOMMU IVHD type. */
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bool iotlb; /* IOTLB supported by IOMMU */
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struct amdvi_cmd *cmd; /* Command descriptor area. */
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int cmd_max; /* Max number of commands. */
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uint64_t cmp_data; /* Command completion write back. */
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struct amdvi_event *event; /* Event descriptor area. */
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struct resource *event_res; /* Event interrupt resource. */
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void *event_tag; /* Event interrupt tag. */
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int event_max; /* Max number of events. */
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int event_irq;
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int event_rid;
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/* ACPI various flags. */
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uint32_t ivhd_flag; /* ACPI IVHD flag. */
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uint32_t ivhd_feature; /* ACPI v1 Reserved or v2 attribute. */
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uint64_t ext_feature; /* IVHD EFR */
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/* PCI related. */
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uint16_t cap_off; /* PCI Capability offset. */
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uint8_t pci_cap; /* PCI capability. */
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uint16_t pci_seg; /* IOMMU PCI domain/segment. */
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uint16_t pci_rid; /* PCI BDF of IOMMU */
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/* Device range under this IOMMU. */
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uint16_t start_dev_rid; /* First device under this IOMMU. */
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uint16_t end_dev_rid; /* Last device under this IOMMU. */
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/* BIOS provided device configuration for end points. */
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struct ivhd_dev_cfg dev_cfg[10];
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int dev_cfg_cnt;
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/* Software statistics. */
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uint64_t event_intr_cnt; /* Total event INTR count. */
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uint64_t total_cmd; /* Total number of commands. */
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};
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int amdvi_setup_hw(struct amdvi_softc *softc);
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int amdvi_teardown_hw(struct amdvi_softc *softc);
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#endif /* _AMDVI_PRIV_H_ */
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