Support for Pentium events was removed completely in e92a1350b5
.
Don't bump .Dd where we are just removing xrefs.
Reviewed by: emaste
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D31423
534 lines
17 KiB
Groff
534 lines
17 KiB
Groff
.\" Copyright (c) 2014 Hiren Panchasara <hiren@FreeBSD.org>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd April 6, 2017
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.Dt PMC.ATOMSILVERMONT 3
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.Os
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.Sh NAME
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.Nm pmc.atomsilvermont
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.Nd measurement events for
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.Tn Intel
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.Tn Atom Silvermont
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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.Tn Intel
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.Tn Atom Silvermont
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CPUs contain PMCs conforming to version 3 of the
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.Tn Intel
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performance measurement architecture.
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These CPUs contains two classes of PMCs:
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.Bl -tag -width "Li PMC_CLASS_IAP"
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.It Li PMC_CLASS_IAF
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Fixed-function counters that count only one hardware event per counter.
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.It Li PMC_CLASS_IAP
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Programmable counters that may be configured to count one of a defined
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set of hardware events.
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.El
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.Pp
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The number of PMCs available in each class and their widths need to be
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determined at run time by calling
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.Xr pmc_cpuinfo 3 .
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.Pp
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Intel Atom Silvermont PMCs are documented in
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.Rs
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.%B "Intel 64 and IA-32 Intel(R) Architecture Software Developer's Manual"
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.%T "Combined Volumes"
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.%N "Order Number 325462-050US"
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.%D February 2014
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.%Q "Intel Corporation"
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.Re
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.Ss ATOM SILVERMONT FIXED FUNCTION PMCS
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These PMCs and their supported events are documented in
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.Xr pmc.iaf 3 .
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.Ss ATOM SILVERMONT PROGRAMMABLE PMCS
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The programmable PMCs support the following capabilities:
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
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.It PMC_CAP_EDGE Ta Yes
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.It PMC_CAP_INTERRUPT Ta Yes
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.It PMC_CAP_INVERT Ta Yes
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.It PMC_CAP_READ Ta Yes
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.It PMC_CAP_PRECISE Ta \&No
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.It PMC_CAP_SYSTEM Ta Yes
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.It PMC_CAP_TAGGING Ta \&No
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.It PMC_CAP_THRESHOLD Ta Yes
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.It PMC_CAP_USER Ta Yes
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.It PMC_CAP_WRITE Ta Yes
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.El
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.Ss Event Qualifiers
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Event specifiers for these PMCs support the following common
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qualifiers:
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.Bl -tag -width indent
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.It Li any
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Count matching events seen on any logical processor in a package.
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.It Li cmask= Ns Ar value
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Configure the PMC to increment only if the number of configured
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events measured in a cycle is greater than or equal to
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.Ar value .
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.It Li edge
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Configure the PMC to count the number of de-asserted to asserted
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transitions of the conditions expressed by the other qualifiers.
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If specified, the counter will increment only once whenever a
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condition becomes true, irrespective of the number of clocks during
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which the condition remains true.
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.It Li inv
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Invert the sense of comparison when the
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.Dq Li cmask
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qualifier is present, making the counter increment when the number of
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events per cycle is less than the value specified by the
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.Dq Li cmask
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qualifier.
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.It Li os
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Configure the PMC to count events happening at processor privilege
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level 0.
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.It Li usr
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Configure the PMC to count events occurring at privilege levels 1, 2
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or 3.
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.El
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.Pp
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If neither of the
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.Dq Li os
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or
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.Dq Li usr
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qualifiers are specified, the default is to enable both.
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.Pp
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Events that require core-specificity to be specified use a
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additional qualifier
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.Dq Li core= Ns Ar core ,
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where argument
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.Ar core
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is one of:
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.Bl -tag -width indent
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.It Li all
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Measure event conditions on all cores.
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.It Li this
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Measure event conditions on this core.
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.El
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.Pp
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The default is
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.Dq Li this .
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.Pp
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Events that require an agent qualifier to be specified use an
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additional qualifier
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.Dq Li agent= Ns agent ,
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where argument
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.Ar agent
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is one of:
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.Bl -tag -width indent
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.It Li this
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Measure events associated with this bus agent.
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.It Li any
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Measure events caused by any bus agent.
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.El
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.Pp
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The default is
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.Dq Li this .
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.Pp
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Events that require a hardware prefetch qualifier to be specified use an
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additional qualifier
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.Dq Li prefetch= Ns Ar prefetch ,
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where argument
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.Ar prefetch
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is one of:
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.Bl -tag -width "exclude"
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.It Li both
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Include all prefetches.
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.It Li only
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Only count hardware prefetches.
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.It Li exclude
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Exclude hardware prefetches.
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.El
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.Pp
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The default is
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.Dq Li both .
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.Pp
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Events that require a cache coherence qualifier to be specified use an
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additional qualifier
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.Dq Li cachestate= Ns Ar state ,
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where argument
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.Ar state
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contains one or more of the following letters:
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.Bl -tag -width indent
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.It Li e
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Count cache lines in the exclusive state.
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.It Li i
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Count cache lines in the invalid state.
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.It Li m
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Count cache lines in the modified state.
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.It Li s
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Count cache lines in the shared state.
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.El
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.Pp
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The default is
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.Dq Li eims .
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.Pp
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Events that require a snoop response qualifier to be specified use an
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additional qualifier
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.Dq Li snoopresponse= Ns Ar response ,
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where argument
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.Ar response
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comprises of the following keywords separated by
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.Dq +
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signs:
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.Bl -tag -width indent
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.It Li clean
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Measure CLEAN responses.
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.It Li hit
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Measure HIT responses.
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.It Li hitm
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Measure HITM responses.
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.El
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.Pp
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The default is to measure all the above responses.
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.Pp
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Events that require a snoop type qualifier use an additional qualifier
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.Dq Li snooptype= Ns Ar type ,
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where argument
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.Ar type
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comprises the one of the following keywords:
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.Bl -tag -width indent
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.It Li cmp2i
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Measure CMP2I snoops.
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.It Li cmp2s
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Measure CMP2S snoops.
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.El
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.Pp
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The default is to measure both snoops.
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.Ss Event Specifiers (Programmable PMCs)
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Atom Silvermont programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li REHABQ.LD_BLOCK_ST_FORWARD
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.Pq Event 03H , Umask 01H
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The number of retired loads that were
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prohibited from receiving forwarded data from the store
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because of address mismatch.
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.It Li REHABQ.LD_BLOCK_STD_NOTREADY
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.Pq Event 03H , Umask 02H
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The cases where a forward was technically possible,
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but did not occur because the store data was not available
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at the right time.
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.It Li REHABQ.ST_SPLITS
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.Pq Event 03H , Umask 04H
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The number of retire stores that experienced.
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cache line boundary splits.
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.It Li REHABQ.LD_SPLITS
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.Pq Event 03H , Umask 08H
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The number of retire loads that experienced.
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cache line boundary splits.
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.It Li REHABQ.LOCK
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.Pq Event 03H , Umask 10H
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The number of retired memory operations with lock semantics.
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These are either implicit locked instructions such as the
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XCHG instruction or instructions with an explicit LOCK
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prefix (0xF0).
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.It Li REHABQ.STA_FULL
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.Pq Event 03H , Umask 20H
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The number of retired stores that are delayed
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because there is not a store address buffer available.
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.It Li REHABQ.ANY_LD
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.Pq Event 03H , Umask 40H
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The number of load uops reissued from Rehabq.
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.It Li REHABQ.ANY_ST
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.Pq Event 03H , Umask 80H
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The number of store uops reissued from Rehabq.
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.It Li MEM_UOPS_RETIRED.L1_MISS_LOADS
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.Pq Event 04H , Umask 01H
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The number of load ops retired that miss in L1
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Data cache.
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Note that prefetch misses will not be counted.
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.It Li MEM_UOPS_RETIRED.L2_HIT_LOADS
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.Pq Event 04H , Umask 02H
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The number of load micro-ops retired that hit L2.
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.It Li MEM_UOPS_RETIRED.L2_MISS_LOADS
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.Pq Event 04H , Umask 04H
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The number of load micro-ops retired that missed L2.
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.It Li MEM_UOPS_RETIRED.DTLB_MISS_LOADS
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.Pq Event 04H , Umask 08H
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The number of load ops retired that had DTLB miss.
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.It Li MEM_UOPS_RETIRED.UTLB_MISS
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.Pq Event 04H , Umask 10H
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The number of load ops retired that had UTLB miss.
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.It Li MEM_UOPS_RETIRED.HITM
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.Pq Event 04H , Umask 20H
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The number of load ops retired that got data
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from the other core or from the other module.
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.It Li MEM_UOPS_RETIRED.ALL_LOADS
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.Pq Event 04H , Umask 40H
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The number of load ops retired.
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.It Li MEM_UOP_RETIRED.ALL_STORES
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.Pq Event 04H , Umask 80H
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The number of store ops retired.
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.It Li PAGE_WALKS.D_SIDE_CYCLES
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.Pq Event 05H , Umask 01H
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Every cycle when a D-side (walks due to a load) page walk is in progress.
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Page walk duration divided by number of page walks is the average duration of
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page-walks.
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Edge trigger bit must be cleared.
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Set Edge to count the number of page walks.
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.It Li PAGE_WALKS.I_SIDE_CYCLES
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.Pq Event 05H , Umask 02H
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Every cycle when a I-side (walks due to an instruction fetch) page walk is in
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progress.
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Page walk duration divided by number of page walks is the average duration of
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page-walks.
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.It Li PAGE_WALKS.WALKS
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.Pq Event 05H , Umask 03H
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The number of times a data (D) page walk or an instruction (I) page walk is
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completed or started.
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Since a page walk implies a TLB miss, the number of TLB misses can be counted
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by counting the number of pagewalks.
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.It Li LONGEST_LAT_CACHE.MISS
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.Pq Event 2EH , Umask 41H
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the total number of L2 cache references and the number of L2 cache misses
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respectively.
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L3 is not supported in Silvermont microarchitecture.
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.It Li LONGEST_LAT_CACHE.REFERENCE
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.Pq Event 2EH , Umask 4FH
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The number of requests originating from the core that
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references a cache line in the L2 cache.
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L3 is not supported in Silvermont microarchitecture.
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.It Li L2_REJECT_XQ.ALL
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.Pq Event 30H , Umask 00H
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The number of demand and prefetch
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transactions that the L2 XQ rejects due to a full or near full
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condition which likely indicates back pressure from the IDI link.
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The XQ may reject transactions from the L2Q (non-cacheable
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requests), BBS (L2 misses) and WOB (L2 write-back victims)
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.It Li CORE_REJECT_L2Q.ALL
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.Pq Event 31H , Umask 00H
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The number of demand and L1 prefetcher
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requests rejected by the L2Q due to a full or nearly full condition which
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likely indicates back pressure from L2Q.
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It also counts requests that would have gone directly to the XQ, but are
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rejected due to a full or nearly full condition, indicating back pressure from
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the IDI link.
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The L2Q may also reject transactions from a core to insure fairness between
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cores, or to delay a core's dirty eviction when the address conflicts incoming
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external snoops.
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(Note that L2 prefetcher requests that are dropped are not counted by this
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event).
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.It Li CPU_CLK_UNHALTED.CORE_P
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.Pq Event 3CH , Umask 00H
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The number of core cycles while the core is not in a halt state.
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The core enters the halt state when it is running the HLT instruction.
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In mobile systems the core frequency may change from time to time.
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For this reason this event may have a changing ratio with regards to time.
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.It Li CPU_CLK_UNHALTED.REF_P
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.Pq Event 3CH , Umask 01H
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The number of reference cycles that the core is not in a halt state.
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The core enters the halt state when it is running the HLT instruction.
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In mobile systems the core frequency may change from time.
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This event is not affected by core frequency changes but counts as if the core
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is running at the maximum frequency all the time.
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.It Li ICACHE.HIT
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.Pq Event 80H , Umask 01H
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The number of instruction fetches from the instruction cache.
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.It Li ICACHE.MISSES
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.Pq Event 80H , Umask 02H
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The number of instruction fetches that miss the Instruction cache or produce
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memory requests.
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This includes uncacheable fetches.
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An instruction fetch miss is counted only once and not once for every cycle
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it is outstanding.
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.It Li ICACHE.ACCESSES
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.Pq Event 80H , Umask 03H
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The number of instruction fetches, including uncacheable fetches.
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.It Li NIP_STALL.ICACHE_MISS
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.Pq Event B6H , Umask 04H
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The number of cycles the NIP stalls because of an icache miss.
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This is a cumulative count of cycles the NIP stalled for all
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icache misses.
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.It Li OFFCORE_RESPONSE_0
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.Pq Event B7H , Umask 01H
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Requires MSR_OFFCORE_RESP0 to specify request type and response.
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.It Li OFFCORE_RESPONSE_1
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.Pq Event B7H , Umask 02H
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Requires MSR_OFFCORE_RESP to specify request type and response.
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.It Li INST_RETIRED.ANY_P
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.Pq Event C0H , Umask 00H
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The number of instructions that retire execution.
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For instructions that consist of multiple micro-ops, this event counts the
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retirement of the last micro-op of the instruction.
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The counter continues counting during hardware interrupts, traps, and inside
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interrupt handlers.
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.It Li UOPS_RETIRED.MS
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.Pq Event C2H , Umask 01H
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The number of micro-ops retired that were supplied from MSROM.
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.It Li UOPS_RETIRED.ALL
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.Pq Event C2H , Umask 10H
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The number of micro-ops retired.
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.It Li MACHINE_CLEARS.SMC
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.Pq Event C3H , Umask 01H
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The number of times that a program writes to a code section.
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Self-modifying code causes a severe penalty in all Intel
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architecture processors.
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.It Li MACHINE_CLEARS.MEMORY_ORDERING
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.Pq Event C3H , Umask 02H
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The number of times that pipeline was cleared due to memory
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ordering issues.
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.It Li MACHINE_CLEARS.FP_ASSIST
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.Pq Event C3H , Umask 04H
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The number of times that pipeline stalled due to FP operations
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needing assists.
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.It Li MACHINE_CLEARS.ALL
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.Pq Event C3H , Umask 08H
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The number of times that pipeline stalled due to due to any causes
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(including SMC, MO, FP assist, etc).
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.It Li BR_INST_RETIRED.ALL_BRANCHES
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.Pq Event C4H , Umask 00H
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The number of branch instructions retired.
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.It Li BR_INST_RETIRED.JCC
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.Pq Event C4H , Umask 7EH
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The number of branch instructions retired that were conditional
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jumps.
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.It Li BR_INST_RETIRED.FAR_BRANCH
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.Pq Event C4H , Umask BFH
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The number of far branch instructions retired.
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.It Li BR_INST_RETIRED.NON_RETURN_IND
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.Pq Event C4H , Umask EBH
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The number of branch instructions retired that were near indirect
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call or near indirect jmp.
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.It Li BR_INST_RETIRED.RETURN
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.Pq Event C4H , Umask F7H
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The number of near RET branch instructions retired.
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.It Li BR_INST_RETIRED.CALL
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.Pq Event C4H , Umask F9H
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The number of near CALL branch instructions retired.
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.It Li BR_INST_RETIRED.IND_CALL
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.Pq Event C4H , Umask FBH
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The number of near indirect CALL branch instructions retired.
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.It Li BR_INST_RETIRED.REL_CALL
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.Pq Event C4H , Umask FDH
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The number of near relative CALL branch instructions retired.
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.It Li BR_INST_RETIRED.TAKEN_JCC
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.Pq Event C4H , Umask FEH
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The number of branch instructions retired that were conditional
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jumps and predicted taken.
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.It Li BR_MISP_RETIRED.ALL_BRANCHES
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.Pq Event C5H , Umask 00H
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The number of mispredicted branch instructions retired.
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.It Li BR_MISP_RETIRED.JCC
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.Pq Event C5H , Umask 7EH
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The number of mispredicted branch instructions retired that were
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conditional jumps.
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.It Li BR_MISP_RETIRED.FAR
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.Pq Event C5H , Umask BFH
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The number of mispredicted far branch instructions retired.
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.It Li BR_MISP_RETIRED.NON_RETURN_IND
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.Pq Event C5H , Umask EBH
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The number of mispredicted branch instructions retired that were
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near indirect call or near indirect jmp.
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.It Li BR_MISP_RETIRED.RETURN
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.Pq Event C5H , Umask F7H
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The number of mispredicted near RET branch instructions retired.
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.It Li BR_MISP_RETIRED.CALL
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.Pq Event C5H , Umask F9H
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The number of mispredicted near CALL branch instructions retired.
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.It Li BR_MISP_RETIRED.IND_CALL
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.Pq Event C5H , Umask FBH
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The number of mispredicted near indirect CALL branch instructions
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retired.
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.It Li BR_MISP_RETIRED.REL_CALL
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.Pq Event C5H , Umask FDH
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The number of mispredicted near relative CALL branch instructions
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retired.
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.It Li BR_MISP_RETIRED.TAKEN_JCC
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.Pq Event C5H , Umask FEH
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|
The number of mispredicted branch instructions retired that were
|
|
conditional jumps and predicted taken.
|
|
.It Li NO_ALLOC_CYCLES.ROB_FULL
|
|
.Pq Event CAH , Umask 01H
|
|
The number of cycles when no uops are allocated and the ROB is full
|
|
(less than 2 entries available).
|
|
.It Li NO_ALLOC_CYCLES.RAT_STALL
|
|
.Pq Event CAH , Umask 20H
|
|
The number of cycles when no uops are allocated and a RATstall is
|
|
asserted.
|
|
.It Li NO_ALLOC_CYCLES.ALL
|
|
.Pq Event CAH , Umask 3FH
|
|
The number of cycles when the front-end does not provide any
|
|
instructions to be allocated for any reason.
|
|
.It Li NO_ALLOC_CYCLES.NOT_DELIVERED
|
|
.Pq Event CAH , Umask 50H
|
|
The number of cycles when the front-end does not provide any
|
|
instructions to be allocated but the back end is not stalled.
|
|
.It Li RS_FULL_STALL.MEC
|
|
.Pq Event CBH , Umask 01H
|
|
The number of cycles the allocation pipe line stalled due to
|
|
the RS for the MEC cluster is full.
|
|
.It Li RS_FULL_STALL.ALL
|
|
.Pq Event CBH , Umask 1FH
|
|
The number of cycles that the allocation pipe line stalled due
|
|
to any one of the RS is full.
|
|
.It Li CYCLES_DIV_BUSY.ANY
|
|
.Pq Event CDH , Umask 01H
|
|
The number of cycles the divider is busy.
|
|
.It Li BACLEARS.ALL
|
|
.Pq Event E6H , Umask 01H
|
|
The number of baclears for any type of branch.
|
|
.It Li BACLEARS.RETURN
|
|
.Pq Event E6H , Umask 08H
|
|
The number of baclears for return branches.
|
|
.It Li BACLEARS.COND
|
|
.Pq Event E6H , Umask 10H
|
|
The number of baclears for conditional branches.
|
|
.It Li MS_DECODED.MS_ENTRY
|
|
.Pq Event E7H , Umask 01H)
|
|
The number of times the MSROM starts a flow of UOPS.
|
|
.El
|
|
.Sh SEE ALSO
|
|
.Xr pmc 3 ,
|
|
.Xr pmc.atom 3 ,
|
|
.Xr pmc.core 3 ,
|
|
.Xr pmc.core2 3 ,
|
|
.Xr pmc.iaf 3 ,
|
|
.Xr pmc.k7 3 ,
|
|
.Xr pmc.k8 3 ,
|
|
.Xr pmc.soft 3 ,
|
|
.Xr pmc.tsc 3 ,
|
|
.Xr pmc_cpuinfo 3 ,
|
|
.Xr pmclog 3 ,
|
|
.Xr hwpmc 4
|
|
.Sh HISTORY
|
|
The
|
|
.Nm pmc
|
|
library first appeared in
|
|
.Fx 6.0 .
|
|
.Sh AUTHORS
|
|
.An -nosplit
|
|
The
|
|
.Lb libpmc
|
|
library was written by
|
|
.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
|
|
The support for the Atom Silvermont
|
|
microarchitecture was written by
|
|
.An Hiren Panchasara Aq Mt hiren@FreeBSD.org .
|