204 lines
6.1 KiB
C
204 lines
6.1 KiB
C
/*
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* Copyright (c) 1997, 1999 Hellmuth Michaelis. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* i4b_ipac.h - definitions for the Siemens IPAC PSB2115 chip
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* ==========================================================
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*
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* $FreeBSD$
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*
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* last edit-date: [Tue Jun 8 09:53:26 1999]
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*
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*---------------------------------------------------------------------------
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*/
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#ifndef _I4B_IPAC_H_
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#define _I4B_IPAC_H_
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#define IPAC_BFIFO_LEN 64 /* 64 bytes B-channel FIFO on chip */
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#define IPAC_HSCXA_OFF 0x00
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#define IPAC_HSCXB_OFF 0x40
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#define IPAC_ISAC_OFF 0x80
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#define IPAC_IPAC_OFF 0xc0
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/* chip version */
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#define IPAC_V11 0x01 /* IPAC Version 1.1 */
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/*
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* definitions of registers and bits for the IPAC ISDN chip.
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*/
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typedef struct ipac_reg {
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/* most registers can be read/written, but have different names */
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/* so define a union with read/write names to make that clear */
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union {
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struct {
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unsigned char ipac_conf;
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unsigned char ipac_ista;
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unsigned char ipac_id;
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unsigned char ipac_acfg;
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unsigned char ipac_aoe;
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unsigned char ipac_arx;
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unsigned char ipac_pita1;
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unsigned char ipac_pita2;
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unsigned char ipac_pota1;
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unsigned char ipac_pota2;
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unsigned char ipac_pcfg;
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unsigned char ipac_scfg;
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unsigned char ipac_timr2;
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} ipac_r;
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struct {
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unsigned char ipac_conf;
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unsigned char ipac_mask;
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unsigned char ipac_dummy;
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unsigned char ipac_acfg;
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unsigned char ipac_aoe;
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unsigned char ipac_atx;
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unsigned char ipac_pita1;
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unsigned char ipac_pita2;
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unsigned char ipac_pota1;
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unsigned char ipac_pota2;
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unsigned char ipac_pcfg;
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unsigned char ipac_scfg;
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unsigned char ipac_timr2;
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} ipac_w;
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} ipac_rw;
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} ipac_reg_t;
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#define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
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/* IPAC read registers */
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#define IPAC_CONF REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_conf)
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#define IPAC_ISTA REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_ista)
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#define IPAC_ID REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_id)
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#define IPAC_ACFG REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_acfg)
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#define IPAC_AOE REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_aoe)
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#define IPAC_ARX REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_arx)
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#define IPAC_PITA1 REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_pita1)
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#define IPAC_PITA2 REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_pita2)
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#define IPAC_POTA1 REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_pota1)
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#define IPAC_POTA2 REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_pota2)
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#define IPAC_PCFG REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_pcfg)
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#define IPAC_SCFG REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_scfg)
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#define IPAC_TIMR2 REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_timr2)
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/* IPAC write registers */
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#define IPAC_MASK REG_OFFSET(ipac_reg_t, ipac_rw.ipac_w.ipac_mask)
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#define IPAC_ATX REG_OFFSET(ipac_reg_t, ipac_rw.ipac_w.ipac_atx)
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/* register bits */
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#define IPAC_CONF_AMP 0x80
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#define IPAC_CONF_CFS 0x40
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#define IPAC_CONF_TEM 0x20
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#define IPAC_CONF_PDS 0x10
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#define IPAC_CONF_IDH 0x08
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#define IPAC_CONF_SGO 0x04
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#define IPAC_CONF_ODS 0x02
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#define IPAC_CONF_IOF 0x01
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#define IPAC_ISTA_INT1 0x80
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#define IPAC_ISTA_INT0 0x40
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#define IPAC_ISTA_ICD 0x20
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#define IPAC_ISTA_EXD 0x10
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#define IPAC_ISTA_ICA 0x08
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#define IPAC_ISTA_EXA 0x04
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#define IPAC_ISTA_ICB 0x02
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#define IPAC_ISTA_EXB 0x01
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#define IPAC_MASK_INT1 0x80
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#define IPAC_MASK_INT0 0x40
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#define IPAC_MASK_ICD 0x20
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#define IPAC_MASK_EXD 0x10
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#define IPAC_MASK_ICA 0x08
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#define IPAC_MASK_EXA 0x04
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#define IPAC_MASK_ICB 0x02
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#define IPAC_MASK_EXB 0x01
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#define IPAC_ACFG_OD7 0x80
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#define IPAC_ACFG_OD6 0x40
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#define IPAC_ACFG_OD5 0x20
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#define IPAC_ACFG_OD4 0x10
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#define IPAC_ACFG_OD3 0x08
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#define IPAC_ACFG_OD2 0x04
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#define IPAC_ACFG_EL1 0x02
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#define IPAC_ACFG_EL2 0x01
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#define IPAC_AOE_OE7 0x80
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#define IPAC_AOE_OE6 0x40
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#define IPAC_AOE_OE5 0x20
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#define IPAC_AOE_OE4 0x10
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#define IPAC_AOE_OE3 0x08
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#define IPAC_AOE_OE2 0x04
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#define IPAC_ARX_AR7 0x80
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#define IPAC_ARX_AR6 0x40
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#define IPAC_ARX_AR5 0x20
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#define IPAC_ARX_AR4 0x10
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#define IPAC_ARX_AR3 0x08
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#define IPAC_ARX_AR2 0x04
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#define IPAC_ATX_AT7 0x80
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#define IPAC_ATX_AT6 0x40
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#define IPAC_ATX_AT5 0x20
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#define IPAC_ATX_AT4 0x10
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#define IPAC_ATX_AT3 0x08
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#define IPAC_ATX_AT2 0x04
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#define IPAC_PITA1_ENA 0x80
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#define IPAC_PITA1_DUDD 0x40
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#define IPAC_PITA2_ENA 0x80
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#define IPAC_PITA2_DUDD 0x40
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#define IPAC_POTA1_ENA 0x80
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#define IPAC_POTA1_DUDD 0x40
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#define IPAC_POTA2_ENA 0x80
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#define IPAC_POTA2_DUDD 0x40
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#define IPAC_PCFG_DPS 0x80
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#define IPAC_PCFG_ACL 0x40
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#define IPAC_PCFG_LED 0x20
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#define IPAC_PCFG_PLD 0x10
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#define IPAC_PCFG_FBS 0x08
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#define IPAC_PCFG_CSL2 0x04
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#define IPAC_PCFG_CSL1 0x02
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#define IPAC_PCFG_CSL0 0x01
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#define IPAC_SCFG_PRI 0x80
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#define IPAC_SCFG_TXD 0x40
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#define IPAC_SCFG_TLEN 0x20
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#define IPAC_TIMR2_TMD 0x80
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#endif /* _I4B_IPAC_H_ */
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