4d892e4f22
The Alpine Platform-On-Chip offers multicore processing (quad ARM Cortex-A15), 1/10Gb Ethernet, SATA 3, PCI-E 3, DMA engines, Virtualization, Advanced Power Management and other. This code drop involves basic platform support including: SMP, IRQs, SerDes, SATA. As of now it is missing the PCIe support. Part of the functionality is provided by the low-level code (HAL) delivered by the chip vendor (Annapurna Labs) and is a subject to change in the future (is planned to be moved to sys/contrib directory). The review log for this commit is available here: https://reviews.freebsd.org/D2340 Reviewed by: andrew, ian, imp Obtained from: Semihalf Sponsored by: Annapurna Labs
149 lines
4.0 KiB
C
149 lines
4.0 KiB
C
/*-
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* Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2015 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/frame.h> /* For trapframe_t, used in <machine/machdep.h> */
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#include <machine/machdep.h>
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#include <machine/pmap.h>
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#include <machine/devmap.h>
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#include <machine/platform.h>
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#include <machine/fdt.h>
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#include <dev/fdt/fdt_common.h>
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#include "opt_ddb.h"
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#include "opt_platform.h"
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struct mtx al_dbg_lock;
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#define DEVMAP_MAX_VA_ADDRESS 0xF0000000
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bus_addr_t al_devmap_pa;
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bus_addr_t al_devmap_size;
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#define AL_NB_SERVICE_OFFSET 0x70000
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#define AL_NB_CCU_OFFSET 0x90000
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#define AL_CCU_SNOOP_CONTROL_IOFAB_0_OFFSET 0x4000
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#define AL_CCU_SNOOP_CONTROL_IOFAB_1_OFFSET 0x5000
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#define AL_CCU_SPECULATION_CONTROL_OFFSET 0x4
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#define AL_NB_ACF_MISC_OFFSET 0xD0
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#define AL_NB_ACF_MISC_READ_BYPASS (1 << 30)
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int alpine_get_devmap_base(bus_addr_t *pa, bus_addr_t *size);
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vm_offset_t
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platform_lastaddr(void)
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{
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return (DEVMAP_MAX_VA_ADDRESS);
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}
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void
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platform_probe_and_attach(void)
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{
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}
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void
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platform_gpio_init(void)
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{
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}
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void
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platform_late_init(void)
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{
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bus_addr_t reg_baddr;
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uint32_t val;
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if (!mtx_initialized(&al_dbg_lock))
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mtx_init(&al_dbg_lock, "ALDBG", "ALDBG", MTX_SPIN);
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/* configure system fabric */
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if (bus_space_map(fdtbus_bs_tag, al_devmap_pa, al_devmap_size, 0,
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®_baddr))
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panic("Couldn't map Register Space area");
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/* do not allow reads to bypass writes to different addresses */
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val = bus_space_read_4(fdtbus_bs_tag, reg_baddr,
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AL_NB_SERVICE_OFFSET + AL_NB_ACF_MISC_OFFSET);
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val &= ~AL_NB_ACF_MISC_READ_BYPASS;
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bus_space_write_4(fdtbus_bs_tag, reg_baddr,
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AL_NB_SERVICE_OFFSET + AL_NB_ACF_MISC_OFFSET, val);
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/* enable cache snoop */
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bus_space_write_4(fdtbus_bs_tag, reg_baddr,
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AL_NB_CCU_OFFSET + AL_CCU_SNOOP_CONTROL_IOFAB_0_OFFSET, 1);
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bus_space_write_4(fdtbus_bs_tag, reg_baddr,
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AL_NB_CCU_OFFSET + AL_CCU_SNOOP_CONTROL_IOFAB_1_OFFSET, 1);
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/* disable speculative fetches from masters */
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bus_space_write_4(fdtbus_bs_tag, reg_baddr,
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AL_NB_CCU_OFFSET + AL_CCU_SPECULATION_CONTROL_OFFSET, 7);
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bus_space_unmap(fdtbus_bs_tag, reg_baddr, al_devmap_size);
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}
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/*
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* Construct pmap_devmap[] with DT-derived config data.
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*/
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int
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platform_devmap_init(void)
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{
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alpine_get_devmap_base(&al_devmap_pa, &al_devmap_size);
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arm_devmap_add_entry(al_devmap_pa, al_devmap_size);
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return (0);
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}
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struct arm32_dma_range *
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bus_dma_get_range(void)
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{
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return (NULL);
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}
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int
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bus_dma_get_range_nb(void)
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{
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return (0);
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}
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