add35ed5b8
to check the status property in their probe routines. Simplebus used to only instantiate its children whose status="okay" but that was improper behavior, fixed in r261352. Now that it doesn't check anymore and probes all its children; the children all have to do the check because really only the children know how to properly interpret their status property strings. Right now all existing drivers only understand "okay" versus something- that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
399 lines
9.0 KiB
C
399 lines
9.0 KiB
C
/*-
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* Copyright (c) 2006 Benno Rice.
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* Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
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* Copyright (c) 2012 Semihalf.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
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* from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/cpuset.h>
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#include <sys/ktr.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/cpufunc.h>
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#include <machine/smp.h>
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#include <arm/mv/mvvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/fdt/fdt_common.h>
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#ifdef DEBUG
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#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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#else
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#define debugf(fmt, args...)
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#endif
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#define MPIC_INT_ERR 4
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#define MPIC_INT_MSI 96
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#define IRQ_MASK 0x3ff
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#define MPIC_CTRL 0x0
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#define MPIC_SOFT_INT 0x4
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#define MPIC_SOFT_INT_DRBL1 (1 << 5)
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#define MPIC_ERR_CAUSE 0x20
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#define MPIC_ISE 0x30
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#define MPIC_ICE 0x34
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#define MPIC_IN_DRBL 0x78
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#define MPIC_IN_DRBL_MASK 0x7c
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#define MPIC_CTP 0xb0
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#define MPIC_CTP 0xb0
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#define MPIC_IIACK 0xb4
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#define MPIC_ISM 0xb8
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#define MPIC_ICM 0xbc
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#define MPIC_ERR_MASK 0xec0
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struct mv_mpic_softc {
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device_t sc_dev;
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struct resource * mpic_res[3];
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bus_space_tag_t mpic_bst;
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bus_space_handle_t mpic_bsh;
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bus_space_tag_t cpu_bst;
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bus_space_handle_t cpu_bsh;
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bus_space_tag_t drbl_bst;
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bus_space_handle_t drbl_bsh;
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};
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static struct resource_spec mv_mpic_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_MEMORY, 2, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct mv_mpic_softc *mv_mpic_sc = NULL;
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void mpic_send_ipi(int cpus, u_int ipi);
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static int mv_mpic_probe(device_t);
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static int mv_mpic_attach(device_t);
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uint32_t mv_mpic_get_cause(void);
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uint32_t mv_mpic_get_cause_err(void);
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uint32_t mv_mpic_get_msi(void);
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static void arm_mask_irq_err(uintptr_t);
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static void arm_unmask_irq_err(uintptr_t);
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static void arm_unmask_msi(void);
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#define MPIC_CPU_WRITE(softc, reg, val) \
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bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val))
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#define MPIC_CPU_READ(softc, reg) \
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bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg))
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#define MPIC_DRBL_WRITE(softc, reg, val) \
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bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val))
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#define MPIC_DRBL_READ(softc, reg) \
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bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg))
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static int
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mv_mpic_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "mrvl,mpic"))
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return (ENXIO);
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device_set_desc(dev, "Marvell Integrated Interrupt Controller");
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return (0);
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}
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static int
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mv_mpic_attach(device_t dev)
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{
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struct mv_mpic_softc *sc;
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int error;
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sc = (struct mv_mpic_softc *)device_get_softc(dev);
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if (mv_mpic_sc != NULL)
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return (ENXIO);
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mv_mpic_sc = sc;
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sc->sc_dev = dev;
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error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res);
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if (error) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);
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sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);
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sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]);
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sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]);
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sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]);
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sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]);
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bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
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MPIC_CTRL, 1);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
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arm_unmask_msi();
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return (0);
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}
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static device_method_t mv_mpic_methods[] = {
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DEVMETHOD(device_probe, mv_mpic_probe),
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DEVMETHOD(device_attach, mv_mpic_attach),
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{ 0, 0 }
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};
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static driver_t mv_mpic_driver = {
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"mpic",
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mv_mpic_methods,
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sizeof(struct mv_mpic_softc),
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};
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static devclass_t mv_mpic_devclass;
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DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0);
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int
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arm_get_next_irq(int last)
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{
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u_int irq, next = -1;
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irq = mv_mpic_get_cause() & IRQ_MASK;
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CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq);
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if (irq != IRQ_MASK) {
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if (irq == MPIC_INT_ERR)
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irq = mv_mpic_get_cause_err();
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if (irq == MPIC_INT_MSI)
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irq = mv_mpic_get_msi();
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next = irq;
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}
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CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next);
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return (next);
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}
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/*
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* XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only
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* by ISM/ICM and remove access to ICE in masking operation
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*/
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void
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arm_mask_irq(uintptr_t nb)
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{
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 1);
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if (nb < ERR_IRQ) {
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bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
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MPIC_ICE, nb);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb);
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} else if (nb < MSI_IRQ)
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arm_mask_irq_err(nb);
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}
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static void
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arm_mask_irq_err(uintptr_t nb)
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{
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uint32_t mask;
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uint8_t bit_off;
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bit_off = nb - ERR_IRQ;
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mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
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mask &= ~(1 << bit_off);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
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}
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void
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arm_unmask_irq(uintptr_t nb)
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{
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
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if (nb < ERR_IRQ) {
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bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
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MPIC_ISE, nb);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb);
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} else if (nb < MSI_IRQ)
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arm_unmask_irq_err(nb);
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if (nb == 0)
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff);
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}
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void
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arm_unmask_irq_err(uintptr_t nb)
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{
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uint32_t mask;
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uint8_t bit_off;
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bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
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MPIC_ISE, MPIC_INT_ERR);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR);
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bit_off = nb - ERR_IRQ;
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mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
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mask |= (1 << bit_off);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
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}
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static void
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arm_unmask_msi(void)
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{
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arm_unmask_irq(MPIC_INT_MSI);
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}
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uint32_t
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mv_mpic_get_cause(void)
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{
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return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK));
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}
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uint32_t
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mv_mpic_get_cause_err(void)
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{
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uint32_t err_cause;
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uint8_t bit_off;
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err_cause = bus_space_read_4(mv_mpic_sc->mpic_bst,
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mv_mpic_sc->mpic_bsh, MPIC_ERR_CAUSE);
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if (err_cause)
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bit_off = ffs(err_cause) - 1;
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else
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return (-1);
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debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause);
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return (ERR_IRQ + bit_off);
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}
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uint32_t
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mv_mpic_get_msi(void)
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{
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uint32_t cause;
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uint8_t bit_off;
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cause = MPIC_DRBL_READ(mv_mpic_sc, 0);
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if (cause)
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bit_off = ffs(cause) - 1;
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else
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return (-1);
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debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause);
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cause &= ~(1 << bit_off);
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MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause);
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return (MSI_IRQ + bit_off);
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}
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int
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mv_msi_data(int irq, uint64_t *addr, uint32_t *data)
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{
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u_long phys, base, size;
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phandle_t node;
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int error;
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node = ofw_bus_get_node(mv_mpic_sc->sc_dev);
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/* Get physical addres of register space */
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error = fdt_get_range(OF_parent(node), 0, &phys, &size);
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if (error) {
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printf("%s: Cannot get register physical address, err:%d",
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__func__, error);
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return (error);
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}
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/* Get offset of MPIC register space */
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error = fdt_regsize(node, &base, &size);
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if (error) {
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printf("%s: Cannot get MPIC register offset, err:%d",
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__func__, error);
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return (error);
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}
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*addr = phys + base + MPIC_SOFT_INT;
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*data = MPIC_SOFT_INT_DRBL1 | irq;
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return (0);
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}
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#if defined(SMP)
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void
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pic_ipi_send(cpuset_t cpus, u_int ipi)
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{
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uint32_t val, i;
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val = 0x00000000;
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for (i = 0; i < MAXCPU; i++)
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if (CPU_ISSET(i, &cpus))
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val |= (1 << (8 + i));
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val |= ipi;
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bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
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MPIC_SOFT_INT, val);
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}
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int
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pic_ipi_get(int i __unused)
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{
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uint32_t val;
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val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL);
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if (val)
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return (ffs(val) - 1);
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return (0x3ff);
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}
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void
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pic_ipi_clear(int ipi)
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{
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uint32_t val;
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val = ~(1 << ipi);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, val);
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}
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#endif
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