670a090971
Fix message ring send path: - define msgrng_access_enable() which disables local interrupts and enables message ring access. Also define msgrng_restore() which restores interrupts - remove all other msgrng enable/disable macros, no need of critical_enter and other locking here. - message_send() fixup: re-read status until pending bit clears - message_send_retry() fixup: retry only few times with interrupts disabled - Fix up message_send/message_send_retry callers - call msgrng_access_enable() and msgrng_restore() correctly so that interrupts are not disabled for long. - removed unused and obsolete code from sys/mips/rmi/msgring.h - some style fixes - more later rge.c (XLR GMAC driver): - updated for the message ring changes - remove unused message_send_block() - retry on credit failure, this is not a permanent failure when credits are configured correctly. Add panic if credits are not available to send for a long time.
431 lines
13 KiB
C
431 lines
13 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD
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* $FreeBSD$
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*/
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#ifndef _RMI_MSGRING_H_
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#define _RMI_MSGRING_H_
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/types.h>
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#include <machine/cpuregs.h>
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#include <machine/cpufunc.h>
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#include <mips/rmi/rmi_mips_exts.h>
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#define MSGRNG_TX_BUF_REG 0
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#define MSGRNG_RX_BUF_REG 1
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#define MSGRNG_MSG_STATUS_REG 2
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#define MSGRNG_MSG_CONFIG_REG 3
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#define MSGRNG_MSG_BUCKSIZE_REG 4
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#define MSGRNG_CC_0_REG 16
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#define MSGRNG_CC_1_REG 17
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#define MSGRNG_CC_2_REG 18
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#define MSGRNG_CC_3_REG 19
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#define MSGRNG_CC_4_REG 20
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#define MSGRNG_CC_5_REG 21
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#define MSGRNG_CC_6_REG 22
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#define MSGRNG_CC_7_REG 23
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#define MSGRNG_CC_8_REG 24
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#define MSGRNG_CC_9_REG 25
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#define MSGRNG_CC_10_REG 26
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#define MSGRNG_CC_11_REG 27
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#define MSGRNG_CC_12_REG 28
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#define MSGRNG_CC_13_REG 29
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#define MSGRNG_CC_14_REG 30
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#define MSGRNG_CC_15_REG 31
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/* Station IDs */
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#define MSGRNG_STNID_CPU0 0x00
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#define MSGRNG_STNID_CPU1 0x08
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#define MSGRNG_STNID_CPU2 0x10
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#define MSGRNG_STNID_CPU3 0x18
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#define MSGRNG_STNID_CPU4 0x20
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#define MSGRNG_STNID_CPU5 0x28
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#define MSGRNG_STNID_CPU6 0x30
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#define MSGRNG_STNID_CPU7 0x38
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#define MSGRNG_STNID_XGS0_TX 64
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#define MSGRNG_STNID_XMAC0_00_TX 64
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#define MSGRNG_STNID_XMAC0_01_TX 65
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#define MSGRNG_STNID_XMAC0_02_TX 66
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#define MSGRNG_STNID_XMAC0_03_TX 67
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#define MSGRNG_STNID_XMAC0_04_TX 68
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#define MSGRNG_STNID_XMAC0_05_TX 69
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#define MSGRNG_STNID_XMAC0_06_TX 70
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#define MSGRNG_STNID_XMAC0_07_TX 71
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#define MSGRNG_STNID_XMAC0_08_TX 72
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#define MSGRNG_STNID_XMAC0_09_TX 73
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#define MSGRNG_STNID_XMAC0_10_TX 74
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#define MSGRNG_STNID_XMAC0_11_TX 75
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#define MSGRNG_STNID_XMAC0_12_TX 76
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#define MSGRNG_STNID_XMAC0_13_TX 77
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#define MSGRNG_STNID_XMAC0_14_TX 78
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#define MSGRNG_STNID_XMAC0_15_TX 79
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#define MSGRNG_STNID_XGS1_TX 80
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#define MSGRNG_STNID_XMAC1_00_TX 80
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#define MSGRNG_STNID_XMAC1_01_TX 81
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#define MSGRNG_STNID_XMAC1_02_TX 82
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#define MSGRNG_STNID_XMAC1_03_TX 83
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#define MSGRNG_STNID_XMAC1_04_TX 84
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#define MSGRNG_STNID_XMAC1_05_TX 85
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#define MSGRNG_STNID_XMAC1_06_TX 86
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#define MSGRNG_STNID_XMAC1_07_TX 87
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#define MSGRNG_STNID_XMAC1_08_TX 88
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#define MSGRNG_STNID_XMAC1_09_TX 89
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#define MSGRNG_STNID_XMAC1_10_TX 90
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#define MSGRNG_STNID_XMAC1_11_TX 91
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#define MSGRNG_STNID_XMAC1_12_TX 92
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#define MSGRNG_STNID_XMAC1_13_TX 93
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#define MSGRNG_STNID_XMAC1_14_TX 94
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#define MSGRNG_STNID_XMAC1_15_TX 95
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#define MSGRNG_STNID_GMAC 96
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#define MSGRNG_STNID_GMACJFR_0 96
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#define MSGRNG_STNID_GMACRFR_0 97
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#define MSGRNG_STNID_GMACTX0 98
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#define MSGRNG_STNID_GMACTX1 99
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#define MSGRNG_STNID_GMACTX2 100
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#define MSGRNG_STNID_GMACTX3 101
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#define MSGRNG_STNID_GMACJFR_1 102
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#define MSGRNG_STNID_GMACRFR_1 103
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#define MSGRNG_STNID_DMA 104
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#define MSGRNG_STNID_DMA_0 104
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#define MSGRNG_STNID_DMA_1 105
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#define MSGRNG_STNID_DMA_2 106
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#define MSGRNG_STNID_DMA_3 107
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#define MSGRNG_STNID_XGS0FR 112
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#define MSGRNG_STNID_XMAC0JFR 112
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#define MSGRNG_STNID_XMAC0RFR 113
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#define MSGRNG_STNID_XGS1FR 114
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#define MSGRNG_STNID_XMAC1JFR 114
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#define MSGRNG_STNID_XMAC1RFR 115
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#define MSGRNG_STNID_SEC 120
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#define MSGRNG_STNID_SEC0 120
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#define MSGRNG_STNID_SEC1 121
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#define MSGRNG_STNID_SEC2 122
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#define MSGRNG_STNID_SEC3 123
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#define MSGRNG_STNID_PK0 124
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#define MSGRNG_STNID_SEC_RSA 124
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#define MSGRNG_STNID_SEC_RSVD0 125
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#define MSGRNG_STNID_SEC_RSVD1 126
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#define MSGRNG_STNID_SEC_RSVD2 127
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#define MSGRNG_STNID_GMAC1 80
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#define MSGRNG_STNID_GMAC1_FR_0 81
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#define MSGRNG_STNID_GMAC1_TX0 82
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#define MSGRNG_STNID_GMAC1_TX1 83
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#define MSGRNG_STNID_GMAC1_TX2 84
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#define MSGRNG_STNID_GMAC1_TX3 85
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#define MSGRNG_STNID_GMAC1_FR_1 87
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#define MSGRNG_STNID_GMAC0 96
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#define MSGRNG_STNID_GMAC0_FR_0 97
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#define MSGRNG_STNID_GMAC0_TX0 98
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#define MSGRNG_STNID_GMAC0_TX1 99
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#define MSGRNG_STNID_GMAC0_TX2 100
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#define MSGRNG_STNID_GMAC0_TX3 101
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#define MSGRNG_STNID_GMAC0_FR_1 103
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#define MSGRNG_STNID_CMP_0 108
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#define MSGRNG_STNID_CMP_1 109
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#define MSGRNG_STNID_CMP_2 110
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#define MSGRNG_STNID_CMP_3 111
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#define MSGRNG_STNID_PCIE_0 116
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#define MSGRNG_STNID_PCIE_1 117
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#define MSGRNG_STNID_PCIE_2 118
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#define MSGRNG_STNID_PCIE_3 119
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#define MSGRNG_STNID_XLS_PK0 121
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#define MSGRNG_CODE_MAC 0
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#define MSGRNG_CODE_XGMAC 2
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#define MSGRNG_CODE_SEC 0
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#define MSGRNG_CODE_BOOT_WAKEUP 200
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#define MSGRNG_CODE_SPI4 3
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#define msgrng_read_status() read_c2_register32(MSGRNG_MSG_STATUS_REG, 0)
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#define msgrng_read_config() read_c2_register32(MSGRNG_MSG_CONFIG_REG, 0)
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#define msgrng_write_config(value) write_c2_register32(MSGRNG_MSG_CONFIG_REG, 0, value)
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#define msgrng_read_bucksize(bucket) read_c2_register32(MSGRNG_MSG_BUCKSIZE_REG, bucket)
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#define msgrng_write_bucksize(bucket, value) write_c2_register32(MSGRNG_MSG_BUCKSIZE_REG, bucket, value)
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#define msgrng_read_cc(reg, pri) read_c2_register32(reg, pri)
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#define msgrng_write_cc(reg, value, pri) write_c2_register32(reg, pri, value)
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#define msgrng_load_rx_msg0() read_c2_register64(MSGRNG_RX_BUF_REG, 0)
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#define msgrng_load_rx_msg1() read_c2_register64(MSGRNG_RX_BUF_REG, 1)
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#define msgrng_load_rx_msg2() read_c2_register64(MSGRNG_RX_BUF_REG, 2)
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#define msgrng_load_rx_msg3() read_c2_register64(MSGRNG_RX_BUF_REG, 3)
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#define msgrng_load_tx_msg0(value) write_c2_register64(MSGRNG_TX_BUF_REG, 0, value)
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#define msgrng_load_tx_msg1(value) write_c2_register64(MSGRNG_TX_BUF_REG, 1, value)
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#define msgrng_load_tx_msg2(value) write_c2_register64(MSGRNG_TX_BUF_REG, 2, value)
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#define msgrng_load_tx_msg3(value) write_c2_register64(MSGRNG_TX_BUF_REG, 3, value)
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static inline void
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msgrng_send(unsigned int stid)
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{
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__asm__ volatile (
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".set push\n"
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".set noreorder\n"
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"sync\n"
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// "msgsnd %0\n"
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"move $8, %0\n"
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"c2 0x80001\n"
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".set pop\n"
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:: "r" (stid):"$8"
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);
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}
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static inline void
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msgrng_receive(unsigned int pri)
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{
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__asm__ volatile (
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".set push\n"
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".set noreorder\n"
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// "msgld %0\n"
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"move $8, %0\n"
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"c2 0x80002\n"
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".set pop\n"
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:: "r" (pri):"$8"
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);
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}
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static inline void
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msgrng_wait(unsigned int mask)
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{
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__asm__ volatile (
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".set push\n"
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".set noreorder\n"
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// "msgwait %0\n"
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"move $8, %0\n"
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"c2 0x80003\n"
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".set pop\n"
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:: "r" (mask):"$8"
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);
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}
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static __inline uint32_t
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msgrng_access_enable(void)
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{
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uint32_t sr = mips_rd_status();
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mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_COP_2_BIT);
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return (sr);
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}
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static __inline void
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msgrng_restore(uint32_t sr)
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{
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mips_wr_status(sr);
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}
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struct msgrng_msg {
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__uint64_t msg0;
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__uint64_t msg1;
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__uint64_t msg2;
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__uint64_t msg3;
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};
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static inline void
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message_send_block_fast(int size, unsigned int code, unsigned int stid,
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unsigned long long msg0, unsigned long long msg1,
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unsigned long long msg2, unsigned long long msg3)
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{
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__asm__ __volatile__(".set push\n"
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".set noreorder\n"
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".set mips64\n"
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"dmtc2 %1, $0, 0\n"
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"dmtc2 %2, $0, 1\n"
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"dmtc2 %3, $0, 2\n"
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"dmtc2 %4, $0, 3\n"
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"move $8, %0\n"
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"1: c2 0x80001\n"
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"mfc2 $8, $2\n"
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"andi $8, $8, 0x6\n"
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"bnez $8, 1b\n"
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"move $8, %0\n"
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".set pop\n"
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:
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: "r"(((size - 1) << 16) | (code << 8) | stid), "r"(msg0), "r"(msg1), "r"(msg2), "r"(msg3)
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: "$8"
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);
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}
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#define message_receive_fast(bucket, size, code, stid, msg0, msg1, msg2, msg3) \
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( { unsigned int _status=0, _tmp=0; \
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msgrng_receive(bucket); \
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while ( (_status=msgrng_read_status()) & 0x08) ; \
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_tmp = _status & 0x30; \
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if (__builtin_expect((!_tmp), 1)) { \
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(size)=((_status & 0xc0)>>6)+1; \
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(code)=(_status & 0xff00)>>8; \
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(stid)=(_status & 0x7f0000)>>16; \
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(msg0)=msgrng_load_rx_msg0(); \
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(msg1)=msgrng_load_rx_msg1(); \
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(msg2)=msgrng_load_rx_msg2(); \
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(msg3)=msgrng_load_rx_msg3(); \
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_tmp=0; \
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} \
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_tmp; \
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} )
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static __inline int
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message_send(unsigned int size, unsigned int code,
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unsigned int stid, struct msgrng_msg *msg)
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{
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unsigned int dest = 0;
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unsigned long long status = 0;
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int i = 0;
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msgrng_load_tx_msg0(msg->msg0);
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msgrng_load_tx_msg1(msg->msg1);
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msgrng_load_tx_msg2(msg->msg2);
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msgrng_load_tx_msg3(msg->msg3);
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dest = ((size - 1) << 16) | (code << 8) | (stid);
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msgrng_send(dest);
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/* Wait for the thread pending to clear */
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do {
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status = msgrng_read_status();
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KASSERT(i++ < 10000, ("Too many fails\n"));
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} while ((status & 0x2) != 0);
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/* If there is a credit failure, return error */
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return status & 0x06;
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}
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static __inline int
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message_send_retry(unsigned int size, unsigned int code,
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unsigned int stid, struct msgrng_msg *msg)
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{
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int i, ret;
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/*
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* we are in with interrupt disabled, retrying too many
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* times is not good
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*/
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for (i = 0; i < 16; i++) {
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ret = message_send(size, code, stid, msg);
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if (ret == 0)
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return (0);
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}
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return (1);
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}
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static __inline__ int
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message_receive(int pri, int *size, int *code, int *src_id,
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struct msgrng_msg *msg)
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{
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int res;
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res = message_receive_fast(pri, *size, *code, *src_id,
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msg->msg0, msg->msg1, msg->msg2, msg->msg3);
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return res;
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}
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#define MSGRNG_STN_RX_QSIZE 256
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struct stn_cc {
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unsigned short counters[16][8];
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};
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struct bucket_size {
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unsigned short bucket[128];
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};
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extern struct bucket_size bucket_sizes;
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extern struct stn_cc cc_table_cpu_0;
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extern struct stn_cc cc_table_cpu_1;
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extern struct stn_cc cc_table_cpu_2;
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extern struct stn_cc cc_table_cpu_3;
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extern struct stn_cc cc_table_cpu_4;
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extern struct stn_cc cc_table_cpu_5;
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extern struct stn_cc cc_table_cpu_6;
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extern struct stn_cc cc_table_cpu_7;
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extern struct stn_cc cc_table_xgs_0;
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extern struct stn_cc cc_table_xgs_1;
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extern struct stn_cc cc_table_gmac;
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extern struct stn_cc cc_table_dma;
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extern struct stn_cc cc_table_sec;
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extern struct bucket_size xls_bucket_sizes;
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extern struct stn_cc xls_cc_table_cpu_0;
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extern struct stn_cc xls_cc_table_cpu_1;
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extern struct stn_cc xls_cc_table_cpu_2;
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extern struct stn_cc xls_cc_table_cpu_3;
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extern struct stn_cc xls_cc_table_gmac0;
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extern struct stn_cc xls_cc_table_gmac1;
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extern struct stn_cc xls_cc_table_cmp;
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extern struct stn_cc xls_cc_table_pcie;
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extern struct stn_cc xls_cc_table_dma;
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extern struct stn_cc xls_cc_table_sec;
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/*
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* NOTE: this is not stationid/8, ie the station numbers below are just
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* for internal use
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*/
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enum {
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TX_STN_CPU_0,
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TX_STN_CPU_1,
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TX_STN_CPU_2,
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TX_STN_CPU_3,
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TX_STN_CPU_4,
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TX_STN_CPU_5,
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TX_STN_CPU_6,
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TX_STN_CPU_7,
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TX_STN_GMAC,
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TX_STN_DMA,
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TX_STN_XGS_0,
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TX_STN_XGS_1,
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TX_STN_SAE,
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TX_STN_GMAC0,
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TX_STN_GMAC1,
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TX_STN_CDE,
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TX_STN_PCIE,
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TX_STN_INVALID,
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MAX_TX_STNS
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};
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extern int register_msgring_handler(int major,
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void (*action) (int, int, int, int, struct msgrng_msg *, void *),
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void *dev_id);
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extern void xlr_msgring_cpu_init(void);
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extern void xlr_msgring_config(void);
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#endif
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