221 lines
6.8 KiB
C
221 lines
6.8 KiB
C
/******************************************************************************
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SPDX-License-Identifier: BSD-3-Clause
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Copyright (c) 2001-2020, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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#include "e1000_hw.h"
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#include "e1000_82575.h"
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#include "e1000_mac.h"
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#include "e1000_base.h"
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#include "e1000_manage.h"
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/**
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* e1000_acquire_phy_base - Acquire rights to access PHY
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* @hw: pointer to the HW structure
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*
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* Acquire access rights to the correct PHY.
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**/
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s32 e1000_acquire_phy_base(struct e1000_hw *hw)
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{
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u16 mask = E1000_SWFW_PHY0_SM;
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DEBUGFUNC("e1000_acquire_phy_base");
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if (hw->bus.func == E1000_FUNC_1)
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mask = E1000_SWFW_PHY1_SM;
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else if (hw->bus.func == E1000_FUNC_2)
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mask = E1000_SWFW_PHY2_SM;
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else if (hw->bus.func == E1000_FUNC_3)
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mask = E1000_SWFW_PHY3_SM;
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return hw->mac.ops.acquire_swfw_sync(hw, mask);
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}
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/**
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* e1000_release_phy_base - Release rights to access PHY
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* @hw: pointer to the HW structure
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*
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* A wrapper to release access rights to the correct PHY.
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**/
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void e1000_release_phy_base(struct e1000_hw *hw)
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{
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u16 mask = E1000_SWFW_PHY0_SM;
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DEBUGFUNC("e1000_release_phy_base");
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if (hw->bus.func == E1000_FUNC_1)
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mask = E1000_SWFW_PHY1_SM;
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else if (hw->bus.func == E1000_FUNC_2)
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mask = E1000_SWFW_PHY2_SM;
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else if (hw->bus.func == E1000_FUNC_3)
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mask = E1000_SWFW_PHY3_SM;
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hw->mac.ops.release_swfw_sync(hw, mask);
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}
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/**
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* e1000_init_hw_base - Initialize hardware
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* @hw: pointer to the HW structure
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*
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* This inits the hardware readying it for operation.
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**/
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s32 e1000_init_hw_base(struct e1000_hw *hw)
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{
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struct e1000_mac_info *mac = &hw->mac;
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s32 ret_val;
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u16 i, rar_count = mac->rar_entry_count;
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DEBUGFUNC("e1000_init_hw_base");
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/* Setup the receive address */
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e1000_init_rx_addrs_generic(hw, rar_count);
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/* Zero out the Multicast HASH table */
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DEBUGOUT("Zeroing the MTA\n");
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for (i = 0; i < mac->mta_reg_count; i++)
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E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
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/* Zero out the Unicast HASH table */
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DEBUGOUT("Zeroing the UTA\n");
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for (i = 0; i < mac->uta_reg_count; i++)
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E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
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/* Setup link and flow control */
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ret_val = mac->ops.setup_link(hw);
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/* Clear all of the statistics registers (clear on read). It is
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* important that we do this after we have tried to establish link
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* because the symbol error count will increment wildly if there
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* is no link.
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*/
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e1000_clear_hw_cntrs_base_generic(hw);
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return ret_val;
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}
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/**
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* e1000_power_down_phy_copper_base - Remove link during PHY power down
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* @hw: pointer to the HW structure
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*
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* In the case of a PHY power down to save power, or to turn off link during a
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* driver unload, or wake on lan is not enabled, remove the link.
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**/
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void e1000_power_down_phy_copper_base(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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if (!(phy->ops.check_reset_block))
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return;
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/* If the management interface is not enabled, then power down */
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if (phy->ops.check_reset_block(hw))
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e1000_power_down_phy_copper(hw);
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}
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/**
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* e1000_rx_fifo_flush_base - Clean Rx FIFO after Rx enable
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* @hw: pointer to the HW structure
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*
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* After Rx enable, if manageability is enabled then there is likely some
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* bad data at the start of the FIFO and possibly in the DMA FIFO. This
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* function clears the FIFOs and flushes any packets that came in as Rx was
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* being enabled.
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**/
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void e1000_rx_fifo_flush_base(struct e1000_hw *hw)
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{
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u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
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int i, ms_wait;
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DEBUGFUNC("e1000_rx_fifo_flush_base");
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/* disable IPv6 options as per hardware errata */
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rfctl = E1000_READ_REG(hw, E1000_RFCTL);
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rfctl |= E1000_RFCTL_IPV6_EX_DIS;
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E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
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if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
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return;
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/* Disable all Rx queues */
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for (i = 0; i < 4; i++) {
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rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
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E1000_WRITE_REG(hw, E1000_RXDCTL(i),
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rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
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}
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/* Poll all queues to verify they have shut down */
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for (ms_wait = 0; ms_wait < 10; ms_wait++) {
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msec_delay(1);
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rx_enabled = 0;
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for (i = 0; i < 4; i++)
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rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
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if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
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break;
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}
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if (ms_wait == 10)
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DEBUGOUT("Queue disable timed out after 10ms\n");
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/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
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* incoming packets are rejected. Set enable and wait 2ms so that
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* any packet that was coming in as RCTL.EN was set is flushed
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*/
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E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
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rlpml = E1000_READ_REG(hw, E1000_RLPML);
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E1000_WRITE_REG(hw, E1000_RLPML, 0);
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rctl = E1000_READ_REG(hw, E1000_RCTL);
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temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
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temp_rctl |= E1000_RCTL_LPE;
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E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
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E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
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E1000_WRITE_FLUSH(hw);
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msec_delay(2);
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/* Enable Rx queues that were previously enabled and restore our
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* previous state
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*/
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for (i = 0; i < 4; i++)
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E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
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E1000_WRITE_REG(hw, E1000_RCTL, rctl);
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E1000_WRITE_FLUSH(hw);
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E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
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E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
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/* Flush receive errors generated by workaround */
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E1000_READ_REG(hw, E1000_ROC);
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E1000_READ_REG(hw, E1000_RNBC);
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E1000_READ_REG(hw, E1000_MPC);
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}
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