205 lines
7.5 KiB
C
205 lines
7.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
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* Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000 BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __PCIB_PRIVATE_H__
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#define __PCIB_PRIVATE_H__
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#include <sys/taskqueue.h>
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#ifdef NEW_PCIB
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/*
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* Data structure and routines that Host to PCI bridge drivers can use
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* to restrict allocations for child devices to ranges decoded by the
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* bridge.
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*/
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struct pcib_host_resources {
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device_t hr_pcib;
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struct resource_list hr_rl;
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};
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int pcib_host_res_init(device_t pcib,
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struct pcib_host_resources *hr);
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int pcib_host_res_free(device_t pcib,
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struct pcib_host_resources *hr);
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int pcib_host_res_decodes(struct pcib_host_resources *hr, int type,
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rman_res_t start, rman_res_t end, u_int flags);
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struct resource *pcib_host_res_alloc(struct pcib_host_resources *hr,
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device_t dev, int type, int *rid, rman_res_t start,
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rman_res_t end, rman_res_t count, u_int flags);
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int pcib_host_res_adjust(struct pcib_host_resources *hr,
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device_t dev, int type, struct resource *r, rman_res_t start,
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rman_res_t end);
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#endif
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/*
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* Export portions of generic PCI:PCI bridge support so that it can be
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* used by subclasses.
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*/
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DECLARE_CLASS(pcib_driver);
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#ifdef NEW_PCIB
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#define WIN_IO 0x1
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#define WIN_MEM 0x2
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#define WIN_PMEM 0x4
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struct pcib_window {
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pci_addr_t base; /* base address */
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pci_addr_t limit; /* topmost address */
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struct rman rman;
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struct resource **res;
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int count; /* size of 'res' array */
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int reg; /* resource id from parent */
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int valid;
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int mask; /* WIN_* bitmask of this window */
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int step; /* log_2 of window granularity */
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const char *name;
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};
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#endif
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struct pcib_secbus {
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u_int sec;
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u_int sub;
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#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
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device_t dev;
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struct rman rman;
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struct resource *res;
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const char *name;
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int sub_reg;
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#endif
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};
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/*
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* Bridge-specific data.
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*/
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struct pcib_softc
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{
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device_t dev;
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device_t child;
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uint32_t flags; /* flags */
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#define PCIB_SUBTRACTIVE 0x1
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#define PCIB_DISABLE_MSI 0x2
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#define PCIB_DISABLE_MSIX 0x4
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#define PCIB_ENABLE_ARI 0x8
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#define PCIB_HOTPLUG 0x10
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#define PCIB_HOTPLUG_CMD_PENDING 0x20
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#define PCIB_DETACH_PENDING 0x40
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#define PCIB_DETACHING 0x80
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u_int domain; /* domain number */
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u_int pribus; /* primary bus number */
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struct pcib_secbus bus; /* secondary bus numbers */
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#ifdef NEW_PCIB
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struct pcib_window io; /* I/O port window */
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struct pcib_window mem; /* memory window */
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struct pcib_window pmem; /* prefetchable memory window */
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#else
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pci_addr_t pmembase; /* base address of prefetchable memory */
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pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
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pci_addr_t membase; /* base address of memory window */
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pci_addr_t memlimit; /* topmost address of memory window */
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uint32_t iobase; /* base address of port window */
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uint32_t iolimit; /* topmost address of port window */
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#endif
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uint16_t bridgectl; /* bridge control register */
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uint16_t pcie_link_sta;
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uint16_t pcie_slot_sta;
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uint32_t pcie_slot_cap;
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struct resource *pcie_mem;
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struct resource *pcie_irq;
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void *pcie_ihand;
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struct task pcie_hp_task;
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struct timeout_task pcie_ab_task;
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struct timeout_task pcie_cc_task;
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struct timeout_task pcie_dll_task;
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struct mtx *pcie_hp_lock;
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};
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#define PCIB_HP_LOCK(sc) mtx_lock((sc)->pcie_hp_lock)
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#define PCIB_HP_UNLOCK(sc) mtx_unlock((sc)->pcie_hp_lock)
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#define PCIB_HP_LOCK_ASSERT(sc) mtx_assert((sc)->pcie_hp_lock, MA_OWNED)
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#define PCIB_SUPPORTED_ARI_VER 1
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typedef uint32_t pci_read_config_fn(int b, int s, int f, int reg, int width);
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int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
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int slot, int func, uint8_t *busnum);
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#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
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struct resource *pci_domain_alloc_bus(int domain, device_t dev, int *rid,
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rman_res_t start, rman_res_t end, rman_res_t count, u_int flags);
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int pci_domain_adjust_bus(int domain, device_t dev,
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struct resource *r, rman_res_t start, rman_res_t end);
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int pci_domain_release_bus(int domain, device_t dev, int rid,
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struct resource *r);
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struct resource *pcib_alloc_subbus(struct pcib_secbus *bus, device_t child,
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int *rid, rman_res_t start, rman_res_t end, rman_res_t count,
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u_int flags);
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void pcib_free_secbus(device_t dev, struct pcib_secbus *bus);
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void pcib_setup_secbus(device_t dev, struct pcib_secbus *bus,
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int min_count);
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#endif
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int pcib_attach(device_t dev);
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int pcib_attach_child(device_t dev);
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void pcib_attach_common(device_t dev);
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void pcib_bridge_init(device_t dev);
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#ifdef NEW_PCIB
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const char *pcib_child_name(device_t child);
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#endif
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int pcib_child_present(device_t dev, device_t child);
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int pcib_detach(device_t dev);
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int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
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int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
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struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
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rman_res_t start, rman_res_t end,
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rman_res_t count, u_int flags);
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#ifdef NEW_PCIB
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int pcib_adjust_resource(device_t bus, device_t child, int type,
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struct resource *r, rman_res_t start, rman_res_t end);
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int pcib_release_resource(device_t dev, device_t child, int type, int rid,
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struct resource *r);
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#endif
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int pcib_maxslots(device_t dev);
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int pcib_maxfuncs(device_t dev);
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int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
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int pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs);
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int pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs);
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int pcib_alloc_msix(device_t pcib, device_t dev, int *irq);
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int pcib_release_msix(device_t pcib, device_t dev, int irq);
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int pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data);
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int pcib_get_id(device_t pcib, device_t dev, enum pci_id_type type,
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uintptr_t *id);
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void pcib_decode_rid(device_t pcib, uint16_t rid, int *bus,
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int *slot, int *func);
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int pcib_request_feature(device_t dev, enum pci_feature feature);
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int pcib_request_feature_allow(device_t pcib, device_t dev, enum pci_feature feature);
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#endif
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