7952584606
This driver supports all the DEC EtherWORKS III NICs (DE203, DE204, and DE205) and the later DEC EtherWORKS II NICs (DE200, DE201, DE202, DE422). DEPCA-style boards prior to the DE200 have not been tested and may not work. Submitted by: Matt Thomas (thomas@lkg.dec.com)
110 lines
4.2 KiB
C
110 lines
4.2 KiB
C
/*
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* AMD 7990 (LANCE) definitions
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*
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*
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*/
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#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
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#define LN_BITFIELD2(a, b) b, a
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#define LN_BITFIELD3(a, b, c) c, b, a
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#define LN_BITFIELD4(a, b, c, d) d, c, b, a
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#else
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#define LN_BITFIELD2(a, b) a, b
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#define LN_BITFIELD3(a, b, c) a, b, c
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#define LN_BITFIELD4(a, b, c, d) a, b, c, d
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#endif
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#define LN_ADDR_LO(addr) ((addr) & 0xFFFF)
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#define LN_ADDR_HI(addr) (((addr) >> 16) & 0xFF)
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typedef struct {
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unsigned short r_addr_lo;
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unsigned short LN_BITFIELD3(r_addr_hi : 8,
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: 5,
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r_log2_size : 3);
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} ln_ring_t;
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#define LN_MC_MASK 0x3F /* Only 6 bits of the CRC */
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typedef struct {
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unsigned short ln_mode;
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#define LN_MODE_RXD 0x0001 /* ( W) Receiver Disabled */
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#define LN_MODE_TXD 0x0002 /* ( W) Transmitter Disabled */
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#define LN_MODE_LOOP 0x0004 /* ( W) Enable Loopback */
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#define LN_MODE_NOTXCRC 0x0008 /* ( W) Don't Calculate TX CRCs */
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#define LN_MODE_FRCCOLL 0x0010 /* ( W) Force Collision */
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#define LN_MODE_NORETRY 0x0020 /* ( W) No Transmit Retries */
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#define LN_MODE_INTLOOP 0x0040 /* ( W) Internal Loopback */
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#define LN_MODE_PROMISC 0x8000 /* ( W) Promiscious Mode */
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unsigned short ln_physaddr[3];
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unsigned short ln_multi_mask[4];
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ln_ring_t ln_rxring;
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ln_ring_t ln_txring;
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} ln_initb_t;
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typedef struct {
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unsigned short d_addr_lo;
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unsigned char d_addr_hi;
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unsigned char d_flag;
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#define LN_DFLAG_EOP 0x0001 /* (RW) End Of Packet */
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#define LN_DFLAG_SOP 0x0002 /* (RW) Start Of Packet */
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#define LN_DFLAG_RxBUFERROR 0x0004 /* (R ) Receive - Buffer Error */
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#define LN_DFLAG_TxDEFERRED 0x0004 /* (R ) Transmit - Initially Deferred */
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#define LN_DFLAG_RxBADCRC 0x0008 /* (R ) Receive - Bad Checksum */
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#define LN_DFLAG_TxONECOLL 0x0008 /* (R ) Transmit - Single Collision */
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#define LN_DFLAG_RxOVERFLOW 0x0010 /* (R ) Receive - Overflow Error */
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#define LN_DFLAG_TxMULTCOLL 0x0010 /* (R ) Transmit - Multiple Collisions */
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#define LN_DFLAG_RxFRAMING 0x0020 /* (R ) Receive - Framing Error */
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#define LN_DFLAG_RxERRSUM 0x0040 /* (R ) Receive - Error Summary */
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#define LN_DFLAG_TxERRSUM 0x0040 /* (R ) Transmit - Error Summary */
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#define LN_DFLAG_OWNER 0x0080 /* (RW) Owner (1=Am7990, 0=host) */
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signed short d_buflen; /* ( W) Two's complement */
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unsigned short d_status;
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#define LN_DSTS_RxLENMASK 0x0FFF /* (R ) Recieve Length */
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#define LN_DSTS_TxTDRMASK 0x03FF /* (R ) Transmit - Time Domain Reflectometer */
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#define LN_DSTS_TxEXCCOLL 0x0400 /* (R ) Transmit - Excessive Collisions */
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#define LN_DSTS_TxCARRLOSS 0x0800 /* (R ) Transmit - Carrier Loss */
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#define LN_DSTS_TxLATECOLL 0x1000 /* (R ) Transmit - Late Collision */
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#define LN_DSTS_TxUNDERFLOW 0x4000 /* (R ) Transmit - Underflow */
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#define LN_DSTS_TxBUFERROR 0x8000 /* (R ) Transmit - Buffer Error */
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} ln_desc_t;
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#define LN_CSR0 0x0000
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#define LN_CSR0_INIT 0x0001 /* (RS) Initialize Am 7990 */
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#define LN_CSR0_START 0x0002 /* (RS) Start Am7990 */
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#define LN_CSR0_STOP 0x0004 /* (RS) Reset Am7990 */
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#define LN_CSR0_TXDEMAND 0x0008 /* (RS) Transmit On Demand */
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#define LN_CSR0_TXON 0x0010 /* (R ) Transmitter Enabled */
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#define LN_CSR0_RXON 0x0020 /* (R ) Receiver Enabled */
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#define LN_CSR0_ENABINTR 0x0040 /* (RW) Interrupt Enabled */
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#define LN_CSR0_PENDINTR 0x0080 /* (R ) Interrupt Pending */
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#define LN_CSR0_INITDONE 0x0100 /* (RC) Initialization Done */
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#define LN_CSR0_TXINT 0x0200 /* (RC) Transmit Interrupt */
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#define LN_CSR0_RXINT 0x0400 /* (RC) Receive Interrupt */
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#define LN_CSR0_MEMERROR 0x0800 /* (RC) Memory Error */
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#define LN_CSR0_MISS 0x1000 /* (RC) No Available Receive Buffers */
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#define LN_CSR0_CERR 0x2000 /* (RC) SQE failed */
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#define LN_CSR0_BABL 0x4000 /* (RC) Transmit Babble */
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#define LN_CSR0_ERRSUM 0x8000 /* (R ) Error Summary (last 4) */
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#define LN_CSR0_CLEAR 0x7F00 /* Clear Status Bit */
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/*
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* CSR1 -- Init Block Address (Low 16 Bits -- Must be Word Aligned)
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* CSR2 -- Init Block Address (High 8 Bits)
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*/
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#define LN_CSR1 0x0001
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#define LN_CSR2 0x0002
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/*
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* CSR3 -- Hardware Control
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*/
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#define LN_CSR3 0x0003
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#define LN_CSR3_BCON 0x0001 /* (RW) BM/HOLD Control */
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#define LN_CSR3_ALE 0x0002 /* (RW) ALE Control */
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#define LN_CSR3_BSWP 0x0004 /* (RW) Byte Swap */
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