d2a72d673f
Right now the only way to set the chainmask is to set the hardware configured chainmask through capabilities. This is fine for forcing the chainmask to be something other than what the hardware is capable of (eg to reduce TX/RX to one connected antenna) but it does change what the HAL hardware chainmask configuration is. For operational mode changes, it (may?) make sense to separately control the TX/RX chainmask. Right now it's done as part of ar5416_reset.c - ar5416UpdateChainMasks() calculates which TX/RX chainmasks to enable based on the operating mode. (1 for legacy and whatever is supported for 11n operation.) But doing this in the HAL is suboptimal - the driver needs to know the currently configured chainmask in order to correctly enable things for each TX descriptor. This is currently done by overriding the chainmask config in the ar5416 TX routines but this has to disappear - the AR9300 HAL support requires the driver to dynamically set the TX chainmask based on the TX power and TX rate in order to meet mini-PCIe slot power requirements. So: * Introduce a new HAL method to set the operational chainmask variables; * Introduce null methods for the previous generation chipsets; * Add new driver state to record the current chainmask separate from the hardware configured chainmask. Part #2 of this will involve disabling ar5416UpdateChainMasks() and moving it into the driver; as well as properly programming the TX chainmask based on the currently configured HAL chainmask. Tested: * AR5416, STA mode - both legacy (11a/11bg) and 11n rates - verified that AR_SELFGEN_MASK (the chainmask used for self-generated frames like ACKs and RTSes) is correct, as well as the TX descriptor contents is correct.
728 lines
17 KiB
C
728 lines
17 KiB
C
/*
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2006 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ar5211/ar5211.h"
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#include "ar5211/ar5211reg.h"
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#include "ar5211/ar5211phy.h"
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#include "ah_eeprom_v3.h"
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#define AR_NUM_GPIO 6 /* 6 GPIO bits */
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#define AR_GPIOD_MASK 0x2f /* 6-bit mask */
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void
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ar5211GetMacAddress(struct ath_hal *ah, uint8_t *mac)
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{
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struct ath_hal_5211 *ahp = AH5211(ah);
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OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
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}
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HAL_BOOL
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ar5211SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
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{
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struct ath_hal_5211 *ahp = AH5211(ah);
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OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
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return AH_TRUE;
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}
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void
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ar5211GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
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{
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static const uint8_t ones[IEEE80211_ADDR_LEN] =
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{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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OS_MEMCPY(mask, ones, IEEE80211_ADDR_LEN);
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}
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HAL_BOOL
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ar5211SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
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{
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return AH_FALSE;
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}
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/*
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* Read 16 bits of data from the specified EEPROM offset.
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*/
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HAL_BOOL
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ar5211EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)
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{
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OS_REG_WRITE(ah, AR_EEPROM_ADDR, off);
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OS_REG_WRITE(ah, AR_EEPROM_CMD, AR_EEPROM_CMD_READ);
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if (!ath_hal_wait(ah, AR_EEPROM_STS,
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AR_EEPROM_STS_READ_COMPLETE | AR_EEPROM_STS_READ_ERROR,
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AR_EEPROM_STS_READ_COMPLETE)) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: read failed for entry 0x%x\n", __func__, off);
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return AH_FALSE;
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}
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*data = OS_REG_READ(ah, AR_EEPROM_DATA) & 0xffff;
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return AH_TRUE;
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}
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#ifdef AH_SUPPORT_WRITE_EEPROM
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/*
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* Write 16 bits of data to the specified EEPROM offset.
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*/
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HAL_BOOL
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ar5211EepromWrite(struct ath_hal *ah, u_int off, uint16_t data)
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{
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return AH_FALSE;
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}
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#endif /* AH_SUPPORT_WRITE_EEPROM */
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/*
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* Attempt to change the cards operating regulatory domain to the given value
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*/
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HAL_BOOL
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ar5211SetRegulatoryDomain(struct ath_hal *ah,
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uint16_t regDomain, HAL_STATUS *status)
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{
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HAL_STATUS ecode;
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if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
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ecode = HAL_EINVAL;
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goto bad;
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}
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/*
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* Check if EEPROM is configured to allow this; must
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* be a proper version and the protection bits must
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* permit re-writing that segment of the EEPROM.
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*/
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if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
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ecode = HAL_EEWRITE;
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goto bad;
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}
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#ifdef AH_SUPPORT_WRITE_REGDOMAIN
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if (ar5211EepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: set regulatory domain to %u (0x%x)\n",
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__func__, regDomain, regDomain);
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AH_PRIVATE(ah)->ah_currentRD = regDomain;
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return AH_TRUE;
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}
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#endif
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ecode = HAL_EIO;
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bad:
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if (status)
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*status = ecode;
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return AH_FALSE;
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}
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/*
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* Return the wireless modes (a,b,g,t) supported by hardware.
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*
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* This value is what is actually supported by the hardware
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* and is unaffected by regulatory/country code settings.
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*
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*/
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u_int
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ar5211GetWirelessModes(struct ath_hal *ah)
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{
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u_int mode = 0;
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if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
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mode = HAL_MODE_11A;
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if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
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mode |= HAL_MODE_TURBO | HAL_MODE_108A;
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}
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if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
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mode |= HAL_MODE_11B;
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return mode;
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}
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#if 0
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HAL_BOOL
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ar5211GetTurboDisable(struct ath_hal *ah)
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{
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return (AH5211(ah)->ah_turboDisable != 0);
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}
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#endif
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/*
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* Called if RfKill is supported (according to EEPROM). Set the interrupt and
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* GPIO values so the ISR and can disable RF on a switch signal
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*/
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void
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ar5211EnableRfKill(struct ath_hal *ah)
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{
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uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
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int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL);
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int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY);
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/*
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* Configure the desired GPIO port for input
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* and enable baseband rf silence.
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*/
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ar5211GpioCfgInput(ah, select);
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OS_REG_SET_BIT(ah, AR_PHY_BASE, 0x00002000);
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/*
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* If radio disable switch connection to GPIO bit x is enabled
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* program GPIO interrupt.
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* If rfkill bit on eeprom is 1, setupeeprommap routine has already
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* verified that it is a later version of eeprom, it has a place for
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* rfkill bit and it is set to 1, indicating that GPIO bit x hardware
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* connection is present.
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*/
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ar5211GpioSetIntr(ah, select, (ar5211GpioGet(ah, select) != polarity));
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}
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/*
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* Configure GPIO Output lines
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*/
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HAL_BOOL
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ar5211GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
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{
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uint32_t reg;
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HALASSERT(gpio < AR_NUM_GPIO);
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reg = OS_REG_READ(ah, AR_GPIOCR);
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reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));
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reg |= AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT);
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OS_REG_WRITE(ah, AR_GPIOCR, reg);
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return AH_TRUE;
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}
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/*
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* Configure GPIO Input lines
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*/
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HAL_BOOL
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ar5211GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
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{
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uint32_t reg;
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HALASSERT(gpio < AR_NUM_GPIO);
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reg = OS_REG_READ(ah, AR_GPIOCR);
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reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));
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reg |= AR_GPIOCR_0_CR_N << (gpio * AR_GPIOCR_CR_SHIFT);
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OS_REG_WRITE(ah, AR_GPIOCR, reg);
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return AH_TRUE;
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}
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/*
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* Once configured for I/O - set output lines
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*/
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HAL_BOOL
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ar5211GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
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{
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uint32_t reg;
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HALASSERT(gpio < AR_NUM_GPIO);
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reg = OS_REG_READ(ah, AR_GPIODO);
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reg &= ~(1 << gpio);
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reg |= (val&1) << gpio;
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OS_REG_WRITE(ah, AR_GPIODO, reg);
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return AH_TRUE;
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}
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/*
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* Once configured for I/O - get input lines
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*/
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uint32_t
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ar5211GpioGet(struct ath_hal *ah, uint32_t gpio)
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{
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if (gpio < AR_NUM_GPIO) {
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uint32_t val = OS_REG_READ(ah, AR_GPIODI);
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val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1;
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return val;
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} else {
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return 0xffffffff;
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}
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}
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/*
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* Set the GPIO 0 Interrupt (gpio is ignored)
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*/
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void
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ar5211GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
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{
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uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
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/* Clear the bits that we will modify. */
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val &= ~(AR_GPIOCR_INT_SEL0 | AR_GPIOCR_INT_SELH | AR_GPIOCR_INT_ENA |
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AR_GPIOCR_0_CR_A);
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val |= AR_GPIOCR_INT_SEL0 | AR_GPIOCR_INT_ENA;
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if (ilevel)
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val |= AR_GPIOCR_INT_SELH;
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/* Don't need to change anything for low level interrupt. */
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OS_REG_WRITE(ah, AR_GPIOCR, val);
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/* Change the interrupt mask. */
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ar5211SetInterrupts(ah, AH5211(ah)->ah_maskReg | HAL_INT_GPIO);
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}
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/*
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* Change the LED blinking pattern to correspond to the connectivity
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*/
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void
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ar5211SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
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{
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static const uint32_t ledbits[8] = {
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AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_PROP, /* HAL_LED_INIT */
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AR_PCICFG_LEDCTL_PEND|AR_PCICFG_LEDMODE_PROP, /* HAL_LED_SCAN */
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AR_PCICFG_LEDCTL_PEND|AR_PCICFG_LEDMODE_PROP, /* HAL_LED_AUTH */
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AR_PCICFG_LEDCTL_ASSOC|AR_PCICFG_LEDMODE_PROP,/* HAL_LED_ASSOC*/
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AR_PCICFG_LEDCTL_ASSOC|AR_PCICFG_LEDMODE_PROP,/* HAL_LED_RUN */
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AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_RAND,
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AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_RAND,
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AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_RAND,
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};
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OS_REG_WRITE(ah, AR_PCICFG,
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(OS_REG_READ(ah, AR_PCICFG) &~
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(AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE))
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| ledbits[state & 0x7]
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);
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}
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/*
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* Change association related fields programmed into the hardware.
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* Writing a valid BSSID to the hardware effectively enables the hardware
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* to synchronize its TSF to the correct beacons and receive frames coming
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* from that BSSID. It is called by the SME JOIN operation.
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*/
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void
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ar5211WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
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{
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struct ath_hal_5211 *ahp = AH5211(ah);
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/* XXX save bssid for possible re-use on reset */
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OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
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OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
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OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
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((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
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}
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/*
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* Get the current hardware tsf for stamlme.
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*/
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uint64_t
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ar5211GetTsf64(struct ath_hal *ah)
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{
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uint32_t low1, low2, u32;
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/* sync multi-word read */
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low1 = OS_REG_READ(ah, AR_TSF_L32);
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u32 = OS_REG_READ(ah, AR_TSF_U32);
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low2 = OS_REG_READ(ah, AR_TSF_L32);
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if (low2 < low1) { /* roll over */
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/*
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* If we are not preempted this will work. If we are
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* then we re-reading AR_TSF_U32 does no good as the
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* low bits will be meaningless. Likewise reading
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* L32, U32, U32, then comparing the last two reads
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* to check for rollover doesn't help if preempted--so
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* we take this approach as it costs one less PCI
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* read which can be noticeable when doing things
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* like timestamping packets in monitor mode.
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*/
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u32++;
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}
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return (((uint64_t) u32) << 32) | ((uint64_t) low2);
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}
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/*
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* Get the current hardware tsf for stamlme.
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*/
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uint32_t
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ar5211GetTsf32(struct ath_hal *ah)
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{
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return OS_REG_READ(ah, AR_TSF_L32);
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}
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/*
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* Reset the current hardware tsf for stamlme
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*/
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void
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ar5211ResetTsf(struct ath_hal *ah)
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{
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uint32_t val = OS_REG_READ(ah, AR_BEACON);
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OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
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}
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/*
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* Grab a semi-random value from hardware registers - may not
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* change often
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*/
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uint32_t
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ar5211GetRandomSeed(struct ath_hal *ah)
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{
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uint32_t nf;
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nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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return (OS_REG_READ(ah, AR_TSF_U32) ^
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OS_REG_READ(ah, AR_TSF_L32) ^ nf);
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}
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/*
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* Detect if our card is present
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*/
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HAL_BOOL
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ar5211DetectCardPresent(struct ath_hal *ah)
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{
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uint16_t macVersion, macRev;
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uint32_t v;
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/*
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* Read the Silicon Revision register and compare that
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* to what we read at attach time. If the same, we say
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* a card/device is present.
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*/
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v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M;
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macVersion = v >> AR_SREV_ID_S;
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macRev = v & AR_SREV_REVISION_M;
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return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
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AH_PRIVATE(ah)->ah_macRev == macRev);
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}
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/*
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* Update MIB Counters
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*/
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void
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ar5211UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats)
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{
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stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
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stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
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stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
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stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
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stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
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}
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HAL_BOOL
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ar5211SetSifsTime(struct ath_hal *ah, u_int us)
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{
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struct ath_hal_5211 *ahp = AH5211(ah);
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if (us > ath_hal_mac_usec(ah, 0xffff)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
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__func__, us);
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ahp->ah_sifstime = (u_int) -1; /* restore default handling */
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return AH_FALSE;
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} else {
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/* convert to system clocks */
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OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us));
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ahp->ah_slottime = us;
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return AH_TRUE;
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}
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}
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u_int
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ar5211GetSifsTime(struct ath_hal *ah)
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{
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u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
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return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
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}
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HAL_BOOL
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ar5211SetSlotTime(struct ath_hal *ah, u_int us)
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{
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struct ath_hal_5211 *ahp = AH5211(ah);
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if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
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__func__, us);
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ahp->ah_slottime = us; /* restore default handling */
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return AH_FALSE;
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} else {
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/* convert to system clocks */
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OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
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ahp->ah_slottime = us;
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return AH_TRUE;
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}
|
|
}
|
|
|
|
u_int
|
|
ar5211GetSlotTime(struct ath_hal *ah)
|
|
{
|
|
u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
|
|
return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5211SetAckTimeout(struct ath_hal *ah, u_int us)
|
|
{
|
|
struct ath_hal_5211 *ahp = AH5211(ah);
|
|
|
|
if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
|
|
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
|
|
__func__, us);
|
|
ahp->ah_acktimeout = (u_int) -1; /* restore default handling */
|
|
return AH_FALSE;
|
|
} else {
|
|
/* convert to system clocks */
|
|
OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
|
|
AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
|
|
ahp->ah_acktimeout = us;
|
|
return AH_TRUE;
|
|
}
|
|
}
|
|
|
|
u_int
|
|
ar5211GetAckTimeout(struct ath_hal *ah)
|
|
{
|
|
u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
|
|
return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
|
|
}
|
|
|
|
u_int
|
|
ar5211GetAckCTSRate(struct ath_hal *ah)
|
|
{
|
|
return ((AH5211(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5211SetAckCTSRate(struct ath_hal *ah, u_int high)
|
|
{
|
|
struct ath_hal_5211 *ahp = AH5211(ah);
|
|
|
|
if (high) {
|
|
OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
|
|
ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB;
|
|
} else {
|
|
OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
|
|
ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB;
|
|
}
|
|
return AH_TRUE;
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5211SetCTSTimeout(struct ath_hal *ah, u_int us)
|
|
{
|
|
struct ath_hal_5211 *ahp = AH5211(ah);
|
|
|
|
if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
|
|
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
|
|
__func__, us);
|
|
ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */
|
|
return AH_FALSE;
|
|
} else {
|
|
/* convert to system clocks */
|
|
OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
|
|
AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
|
|
ahp->ah_ctstimeout = us;
|
|
return AH_TRUE;
|
|
}
|
|
}
|
|
|
|
u_int
|
|
ar5211GetCTSTimeout(struct ath_hal *ah)
|
|
{
|
|
u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
|
|
return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5211SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
|
|
{
|
|
/* nothing to do */
|
|
return AH_TRUE;
|
|
}
|
|
|
|
void
|
|
ar5211SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Control Adaptive Noise Immunity Parameters
|
|
*/
|
|
HAL_BOOL
|
|
ar5211AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
|
|
{
|
|
return AH_FALSE;
|
|
}
|
|
|
|
void
|
|
ar5211AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
|
{
|
|
}
|
|
|
|
void
|
|
ar5211RxMonitor(struct ath_hal *ah, const HAL_NODE_STATS *stats,
|
|
const struct ieee80211_channel *chan)
|
|
{
|
|
}
|
|
|
|
void
|
|
ar5211MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Get the rssi of frame curently being received.
|
|
*/
|
|
uint32_t
|
|
ar5211GetCurRssi(struct ath_hal *ah)
|
|
{
|
|
return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
|
|
}
|
|
|
|
u_int
|
|
ar5211GetDefAntenna(struct ath_hal *ah)
|
|
{
|
|
return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
|
|
}
|
|
|
|
void
|
|
ar5211SetDefAntenna(struct ath_hal *ah, u_int antenna)
|
|
{
|
|
OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
|
|
}
|
|
|
|
HAL_ANT_SETTING
|
|
ar5211GetAntennaSwitch(struct ath_hal *ah)
|
|
{
|
|
return AH5211(ah)->ah_diversityControl;
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5211SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
|
|
{
|
|
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
|
|
|
|
if (chan == AH_NULL) {
|
|
AH5211(ah)->ah_diversityControl = settings;
|
|
return AH_TRUE;
|
|
}
|
|
return ar5211SetAntennaSwitchInternal(ah, settings, chan);
|
|
}
|
|
|
|
HAL_STATUS
|
|
ar5211GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
|
|
uint32_t capability, uint32_t *result)
|
|
{
|
|
|
|
switch (type) {
|
|
case HAL_CAP_CIPHER: /* cipher handled in hardware */
|
|
switch (capability) {
|
|
case HAL_CIPHER_AES_OCB:
|
|
case HAL_CIPHER_WEP:
|
|
case HAL_CIPHER_CLR:
|
|
return HAL_OK;
|
|
default:
|
|
return HAL_ENOTSUPP;
|
|
}
|
|
default:
|
|
return ath_hal_getcapability(ah, type, capability, result);
|
|
}
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5211SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
|
|
uint32_t capability, uint32_t setting, HAL_STATUS *status)
|
|
{
|
|
switch (type) {
|
|
case HAL_CAP_DIAG: /* hardware diagnostic support */
|
|
/*
|
|
* NB: could split this up into virtual capabilities,
|
|
* (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
|
|
* seems worth the additional complexity.
|
|
*/
|
|
#ifdef AH_DEBUG
|
|
AH_PRIVATE(ah)->ah_diagreg = setting;
|
|
#else
|
|
AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
|
|
#endif
|
|
OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
|
|
return AH_TRUE;
|
|
default:
|
|
return ath_hal_setcapability(ah, type, capability,
|
|
setting, status);
|
|
}
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5211GetDiagState(struct ath_hal *ah, int request,
|
|
const void *args, uint32_t argsize,
|
|
void **result, uint32_t *resultsize)
|
|
{
|
|
struct ath_hal_5211 *ahp = AH5211(ah);
|
|
|
|
(void) ahp;
|
|
if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
|
|
return AH_TRUE;
|
|
switch (request) {
|
|
case HAL_DIAG_EEPROM:
|
|
return ath_hal_eepromDiag(ah, request,
|
|
args, argsize, result, resultsize);
|
|
case HAL_DIAG_RFGAIN:
|
|
*result = &ahp->ah_gainValues;
|
|
*resultsize = sizeof(GAIN_VALUES);
|
|
return AH_TRUE;
|
|
case HAL_DIAG_RFGAIN_CURSTEP:
|
|
*result = __DECONST(void *, ahp->ah_gainValues.currStep);
|
|
*resultsize = (*result == AH_NULL) ?
|
|
0 : sizeof(GAIN_OPTIMIZATION_STEP);
|
|
return AH_TRUE;
|
|
}
|
|
return AH_FALSE;
|
|
}
|
|
|
|
/*
|
|
* Return what percentage of the extension channel is busy.
|
|
* This is always disabled for AR5211 series NICs.
|
|
*/
|
|
uint32_t
|
|
ar5211Get11nExtBusy(struct ath_hal *ah)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
|
|
/*
|
|
* There's no channel survey support for the AR5211.
|
|
*/
|
|
HAL_BOOL
|
|
ar5211GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
|
|
{
|
|
|
|
return (AH_FALSE);
|
|
}
|
|
|
|
void
|
|
ar5211SetChainMasks(struct ath_hal *ah, uint32_t txchainmask,
|
|
uint32_t rxchainmask)
|
|
{
|
|
}
|
|
|
|
void
|
|
ar5211EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
|
|
{
|
|
}
|
|
|
|
void
|
|
ar5211GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
|
|
{
|
|
}
|