696ec285aa
Add support for A20 timer. Correct interrupt offset depending from chip. Add basic code for CPU configuration module. For now, add kernel config and dts file (only FDT blob related problem needs to be solved later in order to have one kernel for both cubieboard1 and 2). Approved by: ray@
385 lines
9.6 KiB
C
385 lines
9.6 KiB
C
/*-
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* Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <sys/kdb.h>
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#include "a20/a20_cpu_cfg.h"
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/**
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* Timer registers addr
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*
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*/
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#define SW_TIMER_IRQ_EN_REG 0x00
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#define SW_TIMER_IRQ_STA_REG 0x04
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#define SW_TIMER0_CTRL_REG 0x10
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#define SW_TIMER0_INT_VALUE_REG 0x14
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#define SW_TIMER0_CUR_VALUE_REG 0x18
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#define SW_COUNTER64LO_REG 0xa4
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#define SW_COUNTER64HI_REG 0xa8
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#define CNT64_CTRL_REG 0xa0
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#define CNT64_RL_EN 0x02 /* read latch enable */
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#define TIMER_ENABLE (1<<0)
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#define TIMER_AUTORELOAD (1<<1)
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#define TIMER_OSC24M (1<<2) /* oscillator = 24mhz */
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#define TIMER_PRESCALAR (4<<4) /* prescalar = 16 */
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#define SYS_TIMER_CLKSRC 24000000 /* clock source */
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struct a10_timer_softc {
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device_t sc_dev;
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struct resource *res[2];
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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void *sc_ih; /* interrupt handler */
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uint32_t sc_period;
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uint32_t timer0_freq;
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struct eventtimer et;
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uint8_t sc_timer_type; /* 0 for A10, 1 for A20 */
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};
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int a10_timer_get_timerfreq(struct a10_timer_softc *);
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#define timer_read_4(sc, reg) \
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bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg)
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#define timer_write_4(sc, reg, val) \
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val)
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static u_int a10_timer_get_timecount(struct timecounter *);
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static int a10_timer_timer_start(struct eventtimer *,
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sbintime_t first, sbintime_t period);
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static int a10_timer_timer_stop(struct eventtimer *);
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static uint64_t timer_read_counter64(void);
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static int a10_timer_initialized = 0;
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static int a10_timer_hardclock(void *);
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static int a10_timer_probe(device_t);
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static int a10_timer_attach(device_t);
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static struct timecounter a10_timer_timecounter = {
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.tc_name = "a10_timer timer0",
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.tc_get_timecount = a10_timer_get_timecount,
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.tc_counter_mask = ~0u,
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.tc_frequency = 0,
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.tc_quality = 1000,
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};
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struct a10_timer_softc *a10_timer_sc = NULL;
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static struct resource_spec a10_timer_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static uint64_t
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timer_read_counter64(void)
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{
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uint32_t lo, hi;
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/* In case of A20 get appropriate counter info */
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if (a10_timer_sc->sc_timer_type)
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return (a20_read_counter64());
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/* Latch counter, wait for it to be ready to read. */
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timer_write_4(a10_timer_sc, CNT64_CTRL_REG, CNT64_RL_EN);
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while (timer_read_4(a10_timer_sc, CNT64_CTRL_REG) & CNT64_RL_EN)
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continue;
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hi = timer_read_4(a10_timer_sc, SW_COUNTER64HI_REG);
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lo = timer_read_4(a10_timer_sc, SW_COUNTER64LO_REG);
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return (((uint64_t)hi << 32) | lo);
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}
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static int
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a10_timer_probe(device_t dev)
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{
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struct a10_timer_softc *sc;
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sc = device_get_softc(dev);
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if (ofw_bus_is_compatible(dev, "allwinner,sun4i-timer"))
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sc->sc_timer_type = 0;
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else if (ofw_bus_is_compatible(dev, "allwinner,sun7i-timer"))
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sc->sc_timer_type = 1;
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else
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return (ENXIO);
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device_set_desc(dev, "Allwinner A10/A20 timer");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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a10_timer_attach(device_t dev)
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{
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struct a10_timer_softc *sc;
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int err;
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uint32_t val;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->sc_dev = dev;
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sc->sc_bst = rman_get_bustag(sc->res[0]);
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sc->sc_bsh = rman_get_bushandle(sc->res[0]);
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/* Setup and enable the timer interrupt */
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err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, a10_timer_hardclock,
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NULL, sc, &sc->sc_ih);
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if (err != 0) {
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bus_release_resources(dev, a10_timer_spec, sc->res);
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device_printf(dev, "Unable to setup the clock irq handler, "
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"err = %d\n", err);
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return (ENXIO);
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}
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/* Set clock source to OSC24M, 16 pre-division */
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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val |= TIMER_PRESCALAR | TIMER_OSC24M;
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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/* Enable timer0 */
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val = timer_read_4(sc, SW_TIMER_IRQ_EN_REG);
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val |= TIMER_ENABLE;
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timer_write_4(sc, SW_TIMER_IRQ_EN_REG, val);
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sc->timer0_freq = SYS_TIMER_CLKSRC;
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/* Set desired frequency in event timer and timecounter */
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sc->et.et_frequency = sc->timer0_freq;
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sc->et.et_name = "a10_timer Eventtimer";
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sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
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sc->et.et_quality = 1000;
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sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
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sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
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sc->et.et_start = a10_timer_timer_start;
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sc->et.et_stop = a10_timer_timer_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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if (device_get_unit(dev) == 0)
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a10_timer_sc = sc;
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a10_timer_timecounter.tc_frequency = sc->timer0_freq;
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tc_init(&a10_timer_timecounter);
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if (bootverbose) {
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device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
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device_printf(sc->sc_dev, "event timer clock frequency %u\n",
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sc->timer0_freq);
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device_printf(sc->sc_dev, "timecounter clock frequency %lld\n",
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a10_timer_timecounter.tc_frequency);
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}
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a10_timer_initialized = 1;
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return (0);
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}
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static int
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a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
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sbintime_t period)
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{
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struct a10_timer_softc *sc;
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uint32_t count;
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uint32_t val;
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sc = (struct a10_timer_softc *)et->et_priv;
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if (period != 0)
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sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
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else
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sc->sc_period = 0;
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if (first != 0)
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count = ((uint32_t)et->et_frequency * first) >> 32;
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else
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count = sc->sc_period;
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/* Update timer values */
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timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period);
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timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count);
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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if (period != 0) {
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/* periodic */
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val |= TIMER_AUTORELOAD;
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} else {
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/* oneshot */
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val &= ~TIMER_AUTORELOAD;
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}
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/* Enable timer0 */
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val |= TIMER_ENABLE;
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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return (0);
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}
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static int
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a10_timer_timer_stop(struct eventtimer *et)
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{
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struct a10_timer_softc *sc;
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uint32_t val;
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sc = (struct a10_timer_softc *)et->et_priv;
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/* Disable timer0 */
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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val &= ~TIMER_ENABLE;
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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sc->sc_period = 0;
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return (0);
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}
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int
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a10_timer_get_timerfreq(struct a10_timer_softc *sc)
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{
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return (sc->timer0_freq);
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}
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void
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cpu_initclocks(void)
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{
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cpu_initclocks_bsp();
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}
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static int
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a10_timer_hardclock(void *arg)
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{
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struct a10_timer_softc *sc;
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uint32_t val;
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sc = (struct a10_timer_softc *)arg;
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/* Clear interrupt pending bit. */
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timer_write_4(sc, SW_TIMER_IRQ_STA_REG, 0x1);
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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/*
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* Disabled autoreload and sc_period > 0 means
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* timer_start was called with non NULL first value.
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* Now we will set periodic timer with the given period
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* value.
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*/
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if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
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/* Update timer */
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timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, sc->sc_period);
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/* Make periodic and enable */
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val |= TIMER_AUTORELOAD | TIMER_ENABLE;
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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}
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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return (FILTER_HANDLED);
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}
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u_int
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a10_timer_get_timecount(struct timecounter *tc)
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{
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if (a10_timer_sc == NULL)
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return (0);
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return ((u_int)timer_read_counter64());
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}
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static device_method_t a10_timer_methods[] = {
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DEVMETHOD(device_probe, a10_timer_probe),
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DEVMETHOD(device_attach, a10_timer_attach),
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DEVMETHOD_END
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};
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static driver_t a10_timer_driver = {
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"a10_timer",
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a10_timer_methods,
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sizeof(struct a10_timer_softc),
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};
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static devclass_t a10_timer_devclass;
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DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, a10_timer_devclass, 0, 0);
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void
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DELAY(int usec)
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{
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uint32_t counter;
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uint64_t end, now;
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if (!a10_timer_initialized) {
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for (; usec > 0; usec--)
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for (counter = 50; counter > 0; counter--)
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cpufunc_nullop();
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return;
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}
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now = timer_read_counter64();
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end = now + (a10_timer_sc->timer0_freq / 1000000) * (usec + 1);
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while (now < end)
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now = timer_read_counter64();
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}
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