229 lines
7.2 KiB
C
229 lines
7.2 KiB
C
/*-
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* Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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#define _MV_PCIE_MAX_PORT 8
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#define _MV_PCIE_IO_SIZE (MV_PCIE_IO_SIZE / _MV_PCIE_MAX_PORT)
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#define _MV_PCIE_MEM_SIZE (MV_PCIE_MEM_SIZE / _MV_PCIE_MAX_PORT)
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#define _MV_PCIE_IO(n) (MV_PCIE_IO_BASE + ((n) * _MV_PCIE_IO_SIZE))
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#define _MV_PCIE_MEM(n) (MV_PCIE_MEM_BASE + ((n) * _MV_PCIE_MEM_SIZE))
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#define _MV_PCIE_IO_PHYS(n) (MV_PCIE_IO_PHYS_BASE + ((n) * _MV_PCIE_IO_SIZE))
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#define _MV_PCIE_MEM_PHYS(n) (MV_PCIE_MEM_PHYS_BASE + ((n) * _MV_PCIE_MEM_SIZE))
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/*
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* Note the 'pcib' devices are not declared in the obio_devices[]: due to the
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* much more complex configuration schemes allowed, specifically of the
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* PCI-Express (multiple lanes width per port configured dynamically etc.) it
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* is better and flexible to instantiate the number of PCI bridge devices
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* (known in run-time) in the pcib_mbus_identify() method.
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*/
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struct obio_device obio_devices[] = {
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{ "ic", MV_IC_BASE, MV_IC_SIZE,
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{ -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE,
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{ MV_INT_TIMER0, -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "gpio", MV_GPIO_BASE, MV_GPIO_SIZE,
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{ MV_INT_GPIO7_0, MV_INT_GPIO15_8,
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MV_INT_GPIO23_16, MV_INT_GPIO31_24, -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "uart", MV_UART0_BASE, MV_UART_SIZE,
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{ MV_INT_UART0, -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "uart", MV_UART1_BASE, MV_UART_SIZE,
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{ MV_INT_UART1, -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "idma", MV_IDMA_BASE, MV_IDMA_SIZE,
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{ MV_INT_IDMA_ERR, MV_INT_IDMA0, MV_INT_IDMA1,
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MV_INT_IDMA2, MV_INT_IDMA3, -1 },
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{ -1 },
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CPU_PM_CTRL_IDMA
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},
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{ "xor", MV_XOR_BASE, MV_XOR_SIZE,
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{ MV_INT_XOR0, MV_INT_XOR1,
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MV_INT_XOR_ERR, -1 },
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{ -1 },
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CPU_PM_CTRL_XOR
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},
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{ "ehci", MV_USB0_BASE, MV_USB_SIZE,
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{ MV_INT_USB_ERR, MV_INT_USB0, -1 },
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{ -1 },
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CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2
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},
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{ "mge", MV_ETH0_BASE, MV_ETH_SIZE,
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{ MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC,
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MV_INT_GBESUM, MV_INT_GBE_ERR, -1 },
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{ -1 },
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CPU_PM_CTRL_GE0
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},
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{ "mge", MV_ETH1_BASE, MV_ETH_SIZE,
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{ MV_INT_GBE1RX, MV_INT_GBE1TX, MV_INT_GBE1MISC,
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MV_INT_GBE1SUM, MV_INT_GBE_ERR, -1 },
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{ -1 },
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CPU_PM_CTRL_GE1
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},
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{ "twsi", MV_TWSI_BASE, MV_TWSI_SIZE,
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{ -1 }, { -1 },
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CPU_PM_CTRL_NONE
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},
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{ NULL, 0, 0, { 0 }, { 0 }, 0 }
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};
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const struct obio_pci mv_pci_info[] = {
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{ MV_TYPE_PCIE,
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MV_PCIE00_BASE, MV_PCIE_SIZE,
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_MV_PCIE_IO(0), _MV_PCIE_IO_SIZE, 4, 0xE0,
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_MV_PCIE_MEM(0), _MV_PCIE_MEM_SIZE, 4, 0xE8,
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NULL, MV_INT_PEX00 },
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{ MV_TYPE_PCIE_AGGR_LANE,
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MV_PCIE01_BASE, MV_PCIE_SIZE,
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_MV_PCIE_IO(1), _MV_PCIE_IO_SIZE, 4, 0xD0,
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_MV_PCIE_MEM(1), _MV_PCIE_MEM_SIZE, 4, 0xD8,
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NULL, MV_INT_PEX01 },
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#if 0
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/*
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* XXX Access to devices on this interface (PCIE 0.2) crashes the
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* system. Could be a silicon defect as Marvell U-Boot has a 'Do not
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* touch' precaution comment...
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*/
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{ MV_TYPE_PCIE_AGGR_LANE,
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MV_PCIE02_BASE, MV_PCIE_SIZE,
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_MV_PCIE_IO(2), _MV_PCIE_IO_SIZE(2), 4, 0xB0,
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_MV_PCIE_MEM(2), _MV_PCIE_MEM_SIZE(2), 4, 0xB8,
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NULL, MV_INT_PEX02 },
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#endif
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{ MV_TYPE_PCIE_AGGR_LANE,
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MV_PCIE03_BASE, MV_PCIE_SIZE,
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_MV_PCIE_IO(3), _MV_PCIE_IO_SIZE, 4, 0x70,
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_MV_PCIE_MEM(3), _MV_PCIE_MEM_SIZE, 4, 0x78,
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NULL, MV_INT_PEX03 },
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{ MV_TYPE_PCIE,
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MV_PCIE10_BASE, MV_PCIE_SIZE,
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_MV_PCIE_IO(4), _MV_PCIE_IO_SIZE, 8, 0xE0,
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_MV_PCIE_MEM(4), _MV_PCIE_MEM_SIZE, 8, 0xE8,
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NULL, MV_INT_PEX10 },
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{ MV_TYPE_PCIE_AGGR_LANE,
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MV_PCIE11_BASE, MV_PCIE_SIZE,
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_MV_PCIE_IO(5), _MV_PCIE_IO_SIZE, 8, 0xD0,
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_MV_PCIE_MEM(5), _MV_PCIE_MEM_SIZE, 8, 0xD8,
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NULL, MV_INT_PEX11 },
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{ MV_TYPE_PCIE_AGGR_LANE,
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MV_PCIE12_BASE, MV_PCIE_SIZE,
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_MV_PCIE_IO(6), _MV_PCIE_IO_SIZE, 8, 0xB0,
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_MV_PCIE_MEM(6), _MV_PCIE_MEM_SIZE, 8, 0xB8,
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NULL, MV_INT_PEX12 },
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{ MV_TYPE_PCIE_AGGR_LANE,
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MV_PCIE13_BASE, MV_PCIE_SIZE,
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_MV_PCIE_IO(7), _MV_PCIE_IO_SIZE, 8, 0x70,
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_MV_PCIE_MEM(7), _MV_PCIE_MEM_SIZE, 8, 0x78,
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NULL, MV_INT_PEX13 },
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{ 0, 0, 0 }
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};
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struct resource_spec mv_gpio_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 2, RF_ACTIVE },
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{ SYS_RES_IRQ, 3, RF_ACTIVE },
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{ -1, 0 }
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};
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struct resource_spec mv_xor_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 2, RF_ACTIVE },
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{ -1, 0 }
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};
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const struct decode_win cpu_win_tbl[] = {
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/* Device bus BOOT */
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{ 1, 0x2f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },
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/* Device bus CS0 */
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{ 1, 0x3e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 },
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/* Device bus CS1 */
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{ 1, 0x3d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 },
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/* Device bus CS2 */
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{ 1, 0x3b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 },
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};
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const struct decode_win *cpu_wins = cpu_win_tbl;
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int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win);
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/*
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* Note: the decode windows table for IDMA does not explicitly have DRAM
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* entries, which are not statically defined: active DDR banks (== windows)
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* are established in run time from actual DDR windows settings. All active
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* DDR banks are mapped into IDMA decode windows, so at least one IDMA decode
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* window is occupied by the DDR bank; in case when all (MV_WIN_DDR_MAX)
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* DDR banks are active, the remaining available IDMA decode windows for other
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* targets is only MV_WIN_IDMA_MAX - MV_WIN_DDR_MAX.
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*/
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const struct decode_win idma_win_tbl[] = {
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/* PCIE MEM */
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{ 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1 },
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{ 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1 },
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};
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const struct decode_win *idma_wins = idma_win_tbl;
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int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win);
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