69a5a0bfea
frequency. This counter can be accessed coherently from both cores. Use this as the preferred timecounter for the SWARM kernels. The CP0 COUNT register is unusable as the timecounter on SMP platforms because the COUNT registers on different CPUs are not guaranteed to be in sync.
434 lines
8.6 KiB
C
434 lines
8.6 KiB
C
/*-
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* Copyright (c) 2007 Bruce M. Simpson.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <machine/cpuregs.h>
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#include "opt_ddb.h"
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#include "opt_kdb.h"
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/imgact.h>
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#include <sys/bio.h>
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#include <sys/buf.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/cons.h>
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#include <sys/exec.h>
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#include <sys/ucontext.h>
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#include <sys/proc.h>
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#include <sys/kdb.h>
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#include <sys/ptrace.h>
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#include <sys/reboot.h>
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#include <sys/signalvar.h>
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#include <sys/sysent.h>
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#include <sys/sysproto.h>
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#include <sys/user.h>
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#include <sys/timetc.h>
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#include <vm/vm.h>
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#include <vm/vm_object.h>
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#include <vm/vm_page.h>
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#include <vm/vm_pager.h>
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#include <machine/cache.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <machine/cpuinfo.h>
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#include <machine/cpufunc.h>
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#include <machine/cpuregs.h>
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#include <machine/hwfunc.h>
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#include <machine/intr_machdep.h>
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#include <machine/locore.h>
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#include <machine/md_var.h>
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#include <machine/pte.h>
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#include <machine/sigframe.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#ifdef SMP
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#include <machine/smp.h>
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#endif
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#ifdef CFE
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#include <dev/cfe/cfe_api.h>
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#endif
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#include "sb_scd.h"
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#ifdef DDB
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#ifndef KDB
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#error KDB must be enabled in order for DDB to work!
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#endif
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#endif
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#ifdef CFE_ENV
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extern void cfe_env_init(void);
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#endif
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extern int *edata;
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extern int *end;
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extern char MipsTLBMiss[], MipsTLBMissEnd[];
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void
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platform_cpu_init()
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{
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/* Nothing special */
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}
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static void
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sb_intr_init(int cpuid)
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{
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int intrnum, intsrc;
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/*
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* Disable all sources to the interrupt mapper and setup the mapping
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* between an interrupt source and the mips hard interrupt number.
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*/
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for (intsrc = 0; intsrc < NUM_INTSRC; ++intsrc) {
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intrnum = sb_route_intsrc(intsrc);
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sb_disable_intsrc(cpuid, intsrc);
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sb_write_intmap(cpuid, intsrc, intrnum);
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#ifdef SMP
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/*
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* Set up the mailbox interrupt mapping.
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*
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* The mailbox interrupt is "special" in that it is not shared
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* with any other interrupt source.
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*/
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if (intsrc == INTSRC_MAILBOX3) {
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intrnum = platform_ipi_intrnum();
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sb_write_intmap(cpuid, INTSRC_MAILBOX3, intrnum);
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sb_enable_intsrc(cpuid, INTSRC_MAILBOX3);
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}
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#endif
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}
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}
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static void
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mips_init(void)
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{
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int i, cfe_mem_idx, tmp;
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uint64_t maxmem;
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#ifdef CFE_ENV
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cfe_env_init();
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#endif
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TUNABLE_INT_FETCH("boothowto", &boothowto);
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if (boothowto & RB_VERBOSE)
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bootverbose++;
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#ifdef MAXMEM
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tmp = MAXMEM;
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#else
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tmp = 0;
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#endif
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TUNABLE_INT_FETCH("hw.physmem", &tmp);
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maxmem = (uint64_t)tmp * 1024;
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#ifdef CFE
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/*
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* Query DRAM memory map from CFE.
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*/
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physmem = 0;
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cfe_mem_idx = 0;
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for (i = 0; i < 10; i += 2) {
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int result;
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uint64_t addr, len, type;
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result = cfe_enummem(cfe_mem_idx++, 0, &addr, &len, &type);
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if (result < 0) {
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phys_avail[i] = phys_avail[i + 1] = 0;
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break;
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}
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KASSERT(type == CFE_MI_AVAILABLE,
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("CFE DRAM region is not available?"));
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if (bootverbose)
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printf("cfe_enummem: 0x%016jx/%llu.\n", addr, len);
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if (maxmem != 0) {
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if (addr >= maxmem) {
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printf("Ignoring %llu bytes of memory at 0x%jx "
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"that is above maxmem %dMB\n",
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len, addr,
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(int)(maxmem / (1024 * 1024)));
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continue;
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}
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if (addr + len > maxmem) {
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printf("Ignoring %llu bytes of memory "
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"that is above maxmem %dMB\n",
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(addr + len) - maxmem,
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(int)(maxmem / (1024 * 1024)));
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len = maxmem - addr;
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}
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}
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phys_avail[i] = addr;
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if (i == 0 && addr == 0) {
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/*
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* If this is the first physical memory segment probed
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* from CFE, omit the region at the start of physical
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* memory where the kernel has been loaded.
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*/
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phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
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}
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phys_avail[i + 1] = addr + len;
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physmem += len;
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}
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realmem = btoc(physmem);
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#endif
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physmem = realmem;
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init_param1();
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init_param2(physmem);
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mips_cpu_init();
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/*
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* Sibyte has a L1 data cache coherent with DMA. This includes
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* on-chip network interfaces as well as PCI/HyperTransport bus
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* masters.
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*/
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cpuinfo.cache_coherent_dma = TRUE;
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/*
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* XXX
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* The kernel is running in 32-bit mode but the CFE is running in
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* 64-bit mode. So the SR_KX bit in the status register is turned
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* on by the CFE every time we call into it - for e.g. CFE_CONSOLE.
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*
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* This means that if get a TLB miss for any address above 0xc0000000
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* and the SR_KX bit is set then we will end up in the XTLB exception
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* vector.
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*
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* For now work around this by copying the TLB exception handling
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* code to the XTLB exception vector.
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*/
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{
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bcopy(MipsTLBMiss, (void *)XTLB_MISS_EXC_VEC,
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MipsTLBMissEnd - MipsTLBMiss);
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mips_icache_sync_all();
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mips_dcache_wbinv_all();
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}
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pmap_bootstrap();
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mips_proc0_init();
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mutex_init();
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kdb_init();
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#ifdef KDB
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if (boothowto & RB_KDB)
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kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
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#endif
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}
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void
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platform_halt(void)
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{
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}
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void
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platform_identify(void)
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{
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}
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void
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platform_reset(void)
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{
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/*
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* XXX SMP
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* XXX flush data caches
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*/
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sb_system_reset();
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}
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void
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platform_trap_enter(void)
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{
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}
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void
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platform_trap_exit(void)
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{
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}
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static void
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kseg0_map_coherent(void)
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{
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uint32_t config;
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const int CFG_K0_COHERENT = 5;
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config = mips_rd_config();
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config &= ~CFG_K0_MASK;
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config |= CFG_K0_COHERENT;
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mips_wr_config(config);
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}
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#ifdef SMP
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void
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platform_ipi_send(int cpuid)
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{
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KASSERT(cpuid == 0 || cpuid == 1,
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("platform_ipi_send: invalid cpuid %d", cpuid));
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sb_set_mailbox(cpuid, 1ULL);
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}
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void
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platform_ipi_clear(void)
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{
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int cpuid;
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cpuid = PCPU_GET(cpuid);
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sb_clear_mailbox(cpuid, 1ULL);
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}
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int
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platform_ipi_intrnum(void)
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{
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return (4);
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}
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void
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platform_init_ap(int cpuid)
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{
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KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid));
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/*
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* Make sure that kseg0 is mapped cacheable-coherent
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*/
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kseg0_map_coherent();
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sb_intr_init(cpuid);
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}
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int
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platform_start_ap(int cpuid)
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{
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#ifdef CFE
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int error;
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if ((error = cfe_cpu_start(cpuid, mpentry, 0, 0, 0))) {
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printf("cfe_cpu_start error: %d\n", error);
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return (-1);
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} else {
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return (0);
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}
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#else
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return (-1);
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#endif /* CFE */
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}
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#endif /* SMP */
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static u_int
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sb_get_timecount(struct timecounter *tc)
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{
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return ((u_int)sb_zbbus_cycle_count());
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}
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static void
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sb_timecounter_init(void)
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{
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static struct timecounter sb_timecounter = {
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sb_get_timecount,
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NULL,
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~0u,
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0,
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"sibyte_zbbus_counter",
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2000
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};
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/*
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* The ZBbus cycle counter runs at half the cpu frequency.
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*/
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sb_timecounter.tc_frequency = sb_cpu_speed() / 2;
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platform_timecounter = &sb_timecounter;
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}
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void
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platform_start(__register_t a0, __register_t a1, __register_t a2,
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__register_t a3)
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{
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/*
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* Make sure that kseg0 is mapped cacheable-coherent
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*/
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kseg0_map_coherent();
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/* clear the BSS and SBSS segments */
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memset(&edata, 0, (vm_offset_t)&end - (vm_offset_t)&edata);
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mips_postboot_fixup();
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sb_intr_init(0);
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sb_timecounter_init();
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/* Initialize pcpu stuff */
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mips_pcpu0_init();
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#ifdef CFE
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/*
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* Initialize CFE firmware trampolines before
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* we initialize the low-level console.
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*
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* CFE passes the following values in registers:
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* a0: firmware handle
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* a2: firmware entry point
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* a3: entry point seal
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*/
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if (a3 == CFE_EPTSEAL)
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cfe_init(a0, a2);
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#endif
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cninit();
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mips_init();
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mips_timer_init_params(sb_cpu_speed(), 0);
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set_cputicker(sb_zbbus_cycle_count, sb_cpu_speed() / 2, 1);
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}
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