45d426a34e
mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
204 lines
5.2 KiB
C
204 lines
5.2 KiB
C
/* $OpenBSD: regnum.h,v 1.3 1999/01/27 04:46:06 imp Exp $ */
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/*-
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: reg.h 1.1 90/07/09
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* @(#)reg.h 8.2 (Berkeley) 1/11/94
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* JNPR: regnum.h,v 1.6 2007/08/09 11:23:32 katta
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* $FreeBSD$
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*/
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#ifndef _MACHINE_REGNUM_H_
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#define _MACHINE_REGNUM_H_
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#define STAND_ARG_SIZE 16
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#define STAND_FRAME_SIZE 24
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#define STAND_RA_OFFSET 20
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/* This must match the numbers
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* in pcb.h and is used by
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* swtch.S
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*/
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#define PREG_S0 0
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#define PREG_S1 1
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#define PREG_S2 2
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#define PREG_S3 3
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#define PREG_S4 4
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#define PREG_S5 5
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#define PREG_S6 6
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#define PREG_S7 7
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#define PREG_SP 8
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#define PREG_S8 9
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#define PREG_RA 10
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#define PREG_SR 11
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#define PREG_GP 12
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/*
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* Location of the saved registers relative to ZERO.
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* This must match struct trapframe defined in frame.h exactly.
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*/
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#define ZERO 0
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#define AST 1
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#define V0 2
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#define V1 3
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#define A0 4
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#define A1 5
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#define A2 6
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#define A3 7
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#define T0 8
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#define T1 9
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#define T2 10
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#define T3 11
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#define T4 12
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#define T5 13
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#define T6 14
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#define T7 15
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#define S0 16
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#define S1 17
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#define S2 18
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#define S3 19
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#define S4 20
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#define S5 21
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#define S6 22
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#define S7 23
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#define T8 24
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#define T9 25
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#define K0 26
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#define K1 27
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#define GP 28
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#define SP 29
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#define S8 30
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#define RA 31
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#define SR 32
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#define PS SR /* alias for SR */
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#define MULLO 33
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#define MULHI 34
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#define BADVADDR 35
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#define CAUSE 36
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#define PC 37
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/*
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* IC is valid only on RM7K and RM9K processors. Access to this is
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* controlled by IC_INT_REG which defined in kernel config
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*/
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#define IC 38
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#define DUMMY 39 /* for 8 byte alignment */
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#define NUMSAVEREGS 40
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/*
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* Index of FP registers in 'struct frame', counting from the beginning
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* of the frame (i.e., including the general registers).
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*/
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#define FPBASE NUMSAVEREGS
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#define F0 (FPBASE+0)
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#define F1 (FPBASE+1)
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#define F2 (FPBASE+2)
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#define F3 (FPBASE+3)
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#define F4 (FPBASE+4)
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#define F5 (FPBASE+5)
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#define F6 (FPBASE+6)
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#define F7 (FPBASE+7)
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#define F8 (FPBASE+8)
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#define F9 (FPBASE+9)
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#define F10 (FPBASE+10)
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#define F11 (FPBASE+11)
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#define F12 (FPBASE+12)
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#define F13 (FPBASE+13)
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#define F14 (FPBASE+14)
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#define F15 (FPBASE+15)
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#define F16 (FPBASE+16)
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#define F17 (FPBASE+17)
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#define F18 (FPBASE+18)
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#define F19 (FPBASE+19)
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#define F20 (FPBASE+20)
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#define F21 (FPBASE+21)
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#define F22 (FPBASE+22)
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#define F23 (FPBASE+23)
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#define F24 (FPBASE+24)
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#define F25 (FPBASE+25)
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#define F26 (FPBASE+26)
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#define F27 (FPBASE+27)
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#define F28 (FPBASE+28)
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#define F29 (FPBASE+29)
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#define F30 (FPBASE+30)
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#define F31 (FPBASE+31)
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#define FSR (FPBASE+32)
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#define FSR_DUMMY (FPBASE+33) /* For 8 byte alignment */
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#define NUMFPREGS 34
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#define NREGS (NUMSAVEREGS + NUMFPREGS)
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/*
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* Index of FP registers in 'struct frame', relative to the base
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* of the FP registers in frame (i.e., *not* including the general
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* registers).
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*/
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#define F0_NUM (0)
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#define F1_NUM (1)
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#define F2_NUM (2)
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#define F3_NUM (3)
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#define F4_NUM (4)
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#define F5_NUM (5)
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#define F6_NUM (6)
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#define F7_NUM (7)
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#define F8_NUM (8)
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#define F9_NUM (9)
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#define F10_NUM (10)
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#define F11_NUM (11)
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#define F12_NUM (12)
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#define F13_NUM (13)
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#define F14_NUM (14)
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#define F15_NUM (15)
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#define F16_NUM (16)
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#define F17_NUM (17)
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#define F18_NUM (18)
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#define F19_NUM (19)
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#define F20_NUM (20)
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#define F21_NUM (21)
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#define F22_NUM (22)
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#define F23_NUM (23)
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#define F24_NUM (24)
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#define F25_NUM (25)
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#define F26_NUM (26)
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#define F27_NUM (27)
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#define F28_NUM (28)
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#define F29_NUM (29)
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#define F30_NUM (30)
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#define F31_NUM (31)
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#define FSR_NUM (32)
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#endif /* !_MACHINE_REGNUM_H_ */
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