45d426a34e
mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
96 lines
4.1 KiB
C
96 lines
4.1 KiB
C
/* $OpenBSD$ */
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/*
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* Copyright (c) 2000 Opsycon Open System Consulting AB (www.opsycon.se)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Opsycon Open System
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* Consulting AB, Sweden under contract to QED, Inc.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* JNPR: rm7000.h,v 1.2.4.1 2007/08/29 12:06:30 girish
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* $FreeBSD$
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*/
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#ifndef _MACHINE_RM7000_H_
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#define _MACHINE_RM7000_H_
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/*
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* QED RM7000 specific defines.
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*/
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/*
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* Performance counters.
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*/
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#define PCNT_SRC_CLOCKS 0x00 /* Clock cycles */
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#define PCNT_SRC_INSTR 0x01 /* Total instructions issued */
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#define PCNT_SRC_FPINSTR 0x02 /* Float instructions issued */
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#define PCNT_SRC_IINSTR 0x03 /* Integer instructions issued */
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#define PCNT_SRC_LOAD 0x04 /* Load instructions issued */
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#define PCNT_SRC_STORE 0x05 /* Store instructions issued */
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#define PCNT_SRC_DUAL 0x06 /* Dual issued pairs */
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#define PCNT_SRC_BRPREF 0x07 /* Branch prefetches */
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#define PCNT_SRC_EXTMISS 0x08 /* External cache misses */
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#define PCNT_SRC_STALL 0x09 /* Stall cycles */
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#define PCNT_SRC_SECMISS 0x0a /* Secondary cache misses */
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#define PCNT_SRC_INSMISS 0x0b /* Instruction cache misses */
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#define PCNT_SRC_DTAMISS 0x0c /* Data cache misses */
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#define PCNT_SRC_DTLBMISS 0x0d /* Data TLB misses */
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#define PCNT_SRC_ITLBMISS 0x0e /* Instruction TLB misses */
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#define PCNT_SRC_JTLBIMISS 0x0f /* Joint TLB instruction misses */
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#define PCNT_SRC_JTLBDMISS 0x10 /* Joint TLB data misses */
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#define PCNT_SRC_BRTAKEN 0x11 /* Branches taken */
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#define PCNT_SRC_BRISSUED 0x12 /* Branches issued */
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#define PCNT_SRC_SECWBACK 0x13 /* Secondary cache writebacks */
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#define PCNT_SRC_PRIWBACK 0x14 /* Primary cache writebacks */
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#define PCNT_SRC_DCSTALL 0x15 /* Dcache miss stall cycles */
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#define PCNT_SRC_MISS 0x16 /* Cache misses */
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#define PCNT_SRC_FPEXC 0x17 /* FP possible execption cycles */
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#define PCNT_SRC_MULSLIP 0x18 /* Slip cycles due to mult. busy */
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#define PCNT_SRC_CP0SLIP 0x19 /* CP0 Slip cycles */
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#define PCNT_SRC_LDSLIP 0x1a /* Slip cycles due to pend. non-b ld */
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#define PCNT_SRC_WBFULL 0x1b /* Write buffer full stall cycles */
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#define PCNT_SRC_CISTALL 0x1c /* Cache instruction stall cycles */
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#define PCNT_SRC_MULSTALL 0x1d /* Multiplier stall cycles */
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#define PCNT_SRC_ELDSTALL 0x1d /* Excepion stall due to non-b ld */
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#define PCNT_SRC_MAX 0x1d /* Maximum PCNT select code */
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/*
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* Counter control bits.
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*/
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#define PCNT_CE 0x0400 /* Count enable */
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#define PCNT_UM 0x0200 /* Count in User mode */
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#define PCNT_KM 0x0100 /* Count in kernel mode */
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/*
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* Performance counter system call function codes.
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*/
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#define PCNT_FNC_SELECT 0x0001 /* Select counter source */
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#define PCNT_FNC_READ 0x0002 /* Read current value of counter */
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#endif /* _MACHINE_RM7000_H_ */
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