7239f9f75b
This seems to indicate whether to program the NIC for fractional 5ghz mode (ie, 5mhz spaced channels, rather than 10 or 20mhz spacing) or not. The default (0) seems to mean "only program fractional mode if needed". A different value (eg 1) seems to always enable fractional 5ghz mode regardless of the frequency. Obtained from: Atheros Approved by: re (kib)
293 lines
11 KiB
C
293 lines
11 KiB
C
/*
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* Copyright (c) 2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _AH_EEPROM_V14_H_
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#define _AH_EEPROM_V14_H_
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#include "ah_eeprom.h"
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/* reg_off = 4 * (eep_off) */
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#define AR5416_EEPROM_S 2
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#define AR5416_EEPROM_OFFSET 0x2000
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#define AR5416_EEPROM_START_ADDR 0x503f1200
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#define AR5416_EEPROM_MAX 0xae0 /* Ignore for the moment used only on the flash implementations */
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#define AR5416_EEPROM_MAGIC 0xa55a
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#define AR5416_EEPROM_MAGIC_OFFSET 0x0
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#define owl_get_ntxchains(_txchainmask) \
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(((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
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#ifdef __LINUX_ARM_ARCH__ /* AP71 */
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#define owl_eep_start_loc 0
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#else
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#define owl_eep_start_loc 256
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#endif
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/* End temp defines */
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#define AR5416_EEP_NO_BACK_VER 0x1
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#define AR5416_EEP_VER 0xE
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#define AR5416_EEP_VER_MINOR_MASK 0xFFF
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// Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc
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#define AR5416_EEP_MINOR_VER_2 0x2
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// Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable
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#define AR5416_EEP_MINOR_VER_3 0x3
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#define AR5416_EEP_MINOR_VER_7 0x7
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#define AR5416_EEP_MINOR_VER_9 0x9
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#define AR5416_EEP_MINOR_VER_10 0xa
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#define AR5416_EEP_MINOR_VER_16 0x10
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#define AR5416_EEP_MINOR_VER_17 0x11
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#define AR5416_EEP_MINOR_VER_19 0x13
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#define AR5416_EEP_MINOR_VER_20 0x14
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#define AR5416_EEP_MINOR_VER_21 0x15
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#define AR5416_EEP_MINOR_VER_22 0x16
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// 16-bit offset location start of calibration struct
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#define AR5416_EEP_START_LOC 256
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#define AR5416_NUM_5G_CAL_PIERS 8
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#define AR5416_NUM_2G_CAL_PIERS 4
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#define AR5416_NUM_5G_20_TARGET_POWERS 8
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#define AR5416_NUM_5G_40_TARGET_POWERS 8
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#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
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#define AR5416_NUM_2G_20_TARGET_POWERS 4
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#define AR5416_NUM_2G_40_TARGET_POWERS 4
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#define AR5416_NUM_CTLS 24
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#define AR5416_NUM_BAND_EDGES 8
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#define AR5416_NUM_PD_GAINS 4
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#define AR5416_PD_GAINS_IN_MASK 4
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#define AR5416_PD_GAIN_ICEPTS 5
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#define AR5416_EEPROM_MODAL_SPURS 5
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#define AR5416_MAX_RATE_POWER 63
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#define AR5416_NUM_PDADC_VALUES 128
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#define AR5416_NUM_RATES 16
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#define AR5416_BCHAN_UNUSED 0xFF
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#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
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#define AR5416_EEPMISC_BIG_ENDIAN 0x01
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#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
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#define AR5416_MAX_CHAINS 3
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#define AR5416_PWR_TABLE_OFFSET_DB -5
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#define AR5416_ANT_16S 25
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#define AR5416_NUM_ANT_CHAIN_FIELDS 7
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#define AR5416_NUM_ANT_COMMON_FIELDS 4
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#define AR5416_SIZE_ANT_CHAIN_FIELD 3
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#define AR5416_SIZE_ANT_COMMON_FIELD 4
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#define AR5416_ANT_CHAIN_MASK 0x7
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#define AR5416_ANT_COMMON_MASK 0xf
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#define AR5416_CHAIN_0_IDX 0
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#define AR5416_CHAIN_1_IDX 1
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#define AR5416_CHAIN_2_IDX 2
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#define AR5416_OPFLAGS_11A 0x01
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#define AR5416_OPFLAGS_11G 0x02
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#define AR5416_OPFLAGS_N_5G_HT40 0x04 /* If set, disable 5G HT40 */
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#define AR5416_OPFLAGS_N_2G_HT40 0x08
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#define AR5416_OPFLAGS_N_5G_HT20 0x10
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#define AR5416_OPFLAGS_N_2G_HT20 0x20
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/* RF silent fields in EEPROM */
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#define EEP_RFSILENT_ENABLED 0x0001 /* enabled/disabled */
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#define EEP_RFSILENT_ENABLED_S 0
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#define EEP_RFSILENT_POLARITY 0x0002 /* polarity */
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#define EEP_RFSILENT_POLARITY_S 1
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#define EEP_RFSILENT_GPIO_SEL 0x001c /* gpio PIN */
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#define EEP_RFSILENT_GPIO_SEL_S 2
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/* Rx gain type values */
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#define AR5416_EEP_RXGAIN_23dB_BACKOFF 0
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#define AR5416_EEP_RXGAIN_13dB_BACKOFF 1
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#define AR5416_EEP_RXGAIN_ORIG 2
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/* Tx gain type values */
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#define AR5416_EEP_TXGAIN_ORIG 0
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#define AR5416_EEP_TXGAIN_HIGH_POWER 1
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typedef struct spurChanStruct {
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uint16_t spurChan;
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uint8_t spurRangeLow;
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uint8_t spurRangeHigh;
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} __packed SPUR_CHAN;
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typedef struct CalTargetPowerLegacy {
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uint8_t bChannel;
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uint8_t tPow2x[4];
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} __packed CAL_TARGET_POWER_LEG;
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typedef struct CalTargetPowerHt {
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uint8_t bChannel;
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uint8_t tPow2x[8];
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} __packed CAL_TARGET_POWER_HT;
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typedef struct CalCtlEdges {
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uint8_t bChannel;
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uint8_t tPowerFlag; /* [0..5] tPower [6..7] flag */
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#define CAL_CTL_EDGES_POWER 0x3f
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#define CAL_CTL_EDGES_POWER_S 0
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#define CAL_CTL_EDGES_FLAG 0xc0
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#define CAL_CTL_EDGES_FLAG_S 6
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} __packed CAL_CTL_EDGES;
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/*
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* These are the secondary regulatory domain flags
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* for regDmn[1].
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*/
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#define AR5416_REGDMN_EN_FCC_MID 0x01 /* 5.47 - 5.7GHz operation */
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#define AR5416_REGDMN_EN_JAP_MID 0x02 /* 5.47 - 5.7GHz operation */
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#define AR5416_REGDMN_EN_FCC_DFS_HT40 0x04 /* FCC HT40 + DFS operation */
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#define AR5416_REGDMN_EN_JAP_HT40 0x08 /* JP HT40 operation */
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#define AR5416_REGDMN_EN_JAP_DFS_HT40 0x10 /* JP HT40 + DFS operation */
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/*
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* NB: The format in EEPROM has words 0 and 2 swapped (i.e. version
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* and length are swapped). We reverse their position after reading
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* the data into host memory so the version field is at the same
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* offset as in previous EEPROM layouts. This makes utilities that
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* inspect the EEPROM contents work without looking at the PCI device
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* id which may or may not be reliable.
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*/
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typedef struct BaseEepHeader {
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uint16_t version; /* NB: length in EEPROM */
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uint16_t checksum;
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uint16_t length; /* NB: version in EEPROM */
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uint8_t opCapFlags;
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uint8_t eepMisc;
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uint16_t regDmn[2];
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uint8_t macAddr[6];
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uint8_t rxMask;
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uint8_t txMask;
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uint16_t rfSilent;
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uint16_t blueToothOptions;
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uint16_t deviceCap;
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uint32_t binBuildNumber;
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uint8_t deviceType;
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uint8_t pwdclkind;
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uint8_t fastClk5g;
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uint8_t divChain;
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uint8_t rxGainType;
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uint8_t dacHiPwrMode_5G;/* use the DAC high power mode (MB91) */
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uint8_t openLoopPwrCntl;/* 1: use open loop power control,
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0: use closed loop power control */
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uint8_t dacLpMode;
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uint8_t txGainType; /* high power tx gain table support */
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uint8_t rcChainMask; /* "1" if the card is an HB93 1x2 */
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uint8_t desiredScaleCCK;
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uint8_t pwr_table_offset;
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uint8_t frac_n_5g; /*
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* bit 0: indicates that fracN synth
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* mode applies to all 5G channels
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*/
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uint8_t futureBase[21];
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} __packed BASE_EEP_HEADER; // 64 B
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typedef struct ModalEepHeader {
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uint32_t antCtrlChain[AR5416_MAX_CHAINS]; // 12
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uint32_t antCtrlCommon; // 4
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int8_t antennaGainCh[AR5416_MAX_CHAINS]; // 3
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uint8_t switchSettling; // 1
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uint8_t txRxAttenCh[AR5416_MAX_CHAINS]; // 3
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uint8_t rxTxMarginCh[AR5416_MAX_CHAINS]; // 3
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uint8_t adcDesiredSize; // 1
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int8_t pgaDesiredSize; // 1
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uint8_t xlnaGainCh[AR5416_MAX_CHAINS]; // 3
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uint8_t txEndToXpaOff; // 1
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uint8_t txEndToRxOn; // 1
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uint8_t txFrameToXpaOn; // 1
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uint8_t thresh62; // 1
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uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS]; // 3
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uint8_t xpdGain; // 1
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uint8_t xpd; // 1
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int8_t iqCalICh[AR5416_MAX_CHAINS]; // 1
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int8_t iqCalQCh[AR5416_MAX_CHAINS]; // 1
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uint8_t pdGainOverlap; // 1
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uint8_t ob; // 1
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uint8_t db; // 1
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uint8_t xpaBiasLvl; // 1
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uint8_t pwrDecreaseFor2Chain; // 1
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uint8_t pwrDecreaseFor3Chain; // 1 -> 48 B
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uint8_t txFrameToDataStart; // 1
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uint8_t txFrameToPaOn; // 1
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uint8_t ht40PowerIncForPdadc; // 1
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uint8_t bswAtten[AR5416_MAX_CHAINS]; // 3
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uint8_t bswMargin[AR5416_MAX_CHAINS]; // 3
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uint8_t swSettleHt40; // 1
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uint8_t xatten2Db[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 11:6)
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uint8_t xatten2Margin[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 21:17)
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uint8_t ob_ch1; // 1 -> ob and db become chain specific from AR9280
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uint8_t db_ch1; // 1
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uint8_t flagBits; // 1
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#define AR5416_EEP_FLAG_USEANT1 0x80 /* +1 configured antenna */
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#define AR5416_EEP_FLAG_FORCEXPAON 0x40 /* force XPA bit for 5G */
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#define AR5416_EEP_FLAG_LOCALBIAS 0x20 /* enable local bias */
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#define AR5416_EEP_FLAG_FEMBANDSELECT 0x10 /* FEM band select used */
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#define AR5416_EEP_FLAG_XLNABUFIN 0x08
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#define AR5416_EEP_FLAG_XLNAISEL1 0x04
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#define AR5416_EEP_FLAG_XLNAISEL2 0x02
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#define AR5416_EEP_FLAG_XLNABUFMODE 0x01
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uint8_t miscBits; // [0..1]: bb_tx_dac_scale_cck
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uint16_t xpaBiasLvlFreq[3]; // 3
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uint8_t futureModal[6]; // 6
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SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B
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} __packed MODAL_EEP_HEADER; // == 100 B
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typedef struct calDataPerFreqOpLoop {
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uint8_t pwrPdg[2][5]; /* power measurement */
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uint8_t vpdPdg[2][5]; /* pdadc voltage at power measurement */
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uint8_t pcdac[2][5]; /* pcdac used for power measurement */
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uint8_t empty[2][5]; /* future use */
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} __packed CAL_DATA_PER_FREQ_OP_LOOP;
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typedef struct CalCtlData {
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CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
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} __packed CAL_CTL_DATA;
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typedef struct calDataPerFreq {
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uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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} __packed CAL_DATA_PER_FREQ;
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struct ar5416eeprom {
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BASE_EEP_HEADER baseEepHeader; // 64 B
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uint8_t custData[64]; // 64 B
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MODAL_EEP_HEADER modalHeader[2]; // 200 B
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uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
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uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
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CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
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CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
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CAL_TARGET_POWER_LEG calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
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CAL_TARGET_POWER_HT calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
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CAL_TARGET_POWER_HT calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
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CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
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CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
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CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
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CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
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uint8_t ctlIndex[AR5416_NUM_CTLS];
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CAL_CTL_DATA ctlData[AR5416_NUM_CTLS];
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uint8_t padding;
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} __packed;
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typedef struct {
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struct ar5416eeprom ee_base;
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#define NUM_EDGES 8
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uint16_t ee_numCtls;
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RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_NUM_CTLS];
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/* XXX these are dynamically calculated for use by shared code */
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int8_t ee_antennaGainMax[2];
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} HAL_EEPROM_v14;
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#endif /* _AH_EEPROM_V14_H_ */
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