306 lines
8.2 KiB
C
306 lines
8.2 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/*
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* This product includes software developed by the University of
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* California, Berkeley and its contributors."
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*/
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/* $FreeBSD$ */
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#ifndef __OCTEON_PCMAP_REGS_H__
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#define __OCTEON_PCMAP_REGS_H__
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#ifndef LOCORE
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/*
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* Utility inlines & macros
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*/
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#if defined(__mips_n64)
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#define oct_write64(a, v) (*(volatile uint64_t *)(a) = (uint64_t)(v))
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#define oct_write8_x8(a, v) (*(volatile uint8_t *)(a) = (uint8_t)(v))
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#define OCT_READ(n, t) \
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static inline t oct_read ## n(uintptr_t a) \
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{ \
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volatile t *p = (volatile t *)a; \
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return (*p); \
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}
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OCT_READ(8, uint8_t);
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OCT_READ(16, uint16_t);
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OCT_READ(32, uint32_t);
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OCT_READ(64, uint64_t);
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#elif defined(__mips_n32) || defined(__mips_o32)
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#if defined(__mips_n32)
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static inline void oct_write64 (uint64_t csr_addr, uint64_t val64)
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{
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__asm __volatile (
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".set push\n"
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".set mips64\n"
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"sd %0, 0(%1)\n"
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".set pop\n"
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:
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: "r"(val64), "r"(csr_addr));
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}
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static inline void oct_write8_x8 (uint64_t csr_addr, uint8_t val8)
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{
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__asm __volatile (
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".set push\n"
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".set mips64\n"
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"sb %0, 0(%1)\n"
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".set pop\n"
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:
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: "r"(val8), "r"(csr_addr));
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}
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#define OCT_READ(n, t, insn) \
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static inline t oct_read ## n(uint64_t a) \
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{ \
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uint64_t tmp; \
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\
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__asm __volatile ( \
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".set push\n" \
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".set mips64\n" \
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insn "\t%0, 0(%1)\n" \
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".set pop\n" \
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: "=r"(tmp) \
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: "r"(a)); \
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return ((t)tmp); \
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}
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OCT_READ(8, uint8_t, "lb");
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OCT_READ(16, uint16_t, "lh");
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OCT_READ(32, uint32_t, "lw");
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OCT_READ(64, uint64_t, "ld");
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#else
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/*
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* XXX
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* Add o32 variants that load the address into a register and the result out
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* of a register properly, and simply disable interrupts before and after and
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* hope that we don't need to refill or modify the TLB to access the address.
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* I'd be a lot happier if csr_addr were a physical address and we mapped it
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* into XKPHYS here so that we could guarantee that interrupts were the only
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* kind of exception we needed to worry about.
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*
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* Also, some of this inline assembly is needlessly verbose. Oh, well.
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*/
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static inline void oct_write64 (uint64_t csr_addr, uint64_t val64)
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{
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uint32_t csr_addrh = csr_addr >> 32;
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uint32_t csr_addrl = csr_addr;
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uint32_t valh = val64 >> 32;
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uint32_t vall = val64;
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uint32_t tmp1;
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uint32_t tmp2;
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uint32_t tmp3;
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register_t sr;
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sr = intr_disable();
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__asm __volatile (
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".set push\n"
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".set mips64\n"
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".set noreorder\n"
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".set noat\n"
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"dsll %0, %3, 32\n"
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"dsll %1, %5, 32\n"
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"dsll %2, %4, 32\n"
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"dsrl %2, %2, 32\n"
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"or %0, %0, %2\n"
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"dsll %2, %6, 32\n"
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"dsrl %2, %2, 32\n"
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"or %1, %1, %2\n"
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"sd %0, 0(%1)\n"
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".set pop\n"
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: "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
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: "r" (valh), "r" (vall), "r" (csr_addrh), "r" (csr_addrl));
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intr_restore(sr);
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}
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static inline void oct_write8_x8 (uint64_t csr_addr, uint8_t val8)
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{
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uint32_t csr_addrh = csr_addr >> 32;
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uint32_t csr_addrl = csr_addr;
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uint32_t tmp1;
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uint32_t tmp2;
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register_t sr;
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sr = intr_disable();
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__asm __volatile (
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".set push\n"
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".set mips64\n"
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".set noreorder\n"
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".set noat\n"
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"dsll %0, %3, 32\n"
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"dsll %1, %4, 32\n"
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"dsrl %1, %1, 32\n"
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"or %0, %0, %1\n"
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"sb %2, 0(%0)\n"
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".set pop\n"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r" (val8), "r" (csr_addrh), "r" (csr_addrl));
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intr_restore(sr);
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}
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#define OCT_READ(n, t, insn) \
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static inline t oct_read ## n(uint64_t csr_addr) \
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{ \
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uint32_t csr_addrh = csr_addr >> 32; \
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uint32_t csr_addrl = csr_addr; \
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uint32_t tmp1, tmp2; \
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register_t sr; \
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\
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sr = intr_disable(); \
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\
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__asm __volatile ( \
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".set push\n" \
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".set mips64\n" \
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".set noreorder\n" \
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".set noat\n" \
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"dsll %1, %2, 32\n" \
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"dsll %0, %3, 32\n" \
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"dsrl %0, %0, 32\n" \
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"or %1, %1, %0\n" \
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"lb %1, 0(%1)\n" \
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".set pop\n" \
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: "=&r" (tmp1), "=&r" (tmp2) \
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: "r" (csr_addrh), "r" (csr_addrl)); \
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\
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intr_restore(sr); \
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\
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return ((t)tmp2); \
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}
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OCT_READ(8, uint8_t, "lb");
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OCT_READ(16, uint16_t, "lh");
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OCT_READ(32, uint32_t, "lw");
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static inline uint64_t oct_read64 (uint64_t csr_addr)
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{
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uint32_t csr_addrh = csr_addr >> 32;
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uint32_t csr_addrl = csr_addr;
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uint32_t valh;
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uint32_t vall;
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register_t sr;
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sr = intr_disable();
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__asm __volatile (
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".set push\n"
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".set mips64\n"
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".set noreorder\n"
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".set noat\n"
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"dsll %0, %2, 32\n"
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"dsll %1, %3, 32\n"
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"dsrl %1, %1, 32\n"
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"or %0, %0, %1\n"
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"ld %1, 0(%0)\n"
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"dsrl %0, %1, 32\n"
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"dsll %1, %1, 32\n"
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"dsrl %1, %1, 32\n"
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".set pop\n"
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: "=&r" (valh), "=&r" (vall)
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: "r" (csr_addrh), "r" (csr_addrl));
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intr_restore(sr);
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return ((uint64_t)valh << 32) | vall;
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}
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#endif
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#endif
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#define oct_write64_int64(a, v) (oct_write64(a, (int64_t)(v)))
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/*
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* Most write bus transactions are actually 64-bit on Octeon.
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*/
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static inline void oct_write8 (uint64_t csr_addr, uint8_t val8)
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{
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oct_write64(csr_addr, (uint64_t) val8);
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}
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static inline void oct_write16 (uint64_t csr_addr, uint16_t val16)
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{
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oct_write64(csr_addr, (uint64_t) val16);
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}
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static inline void oct_write32 (uint64_t csr_addr, uint32_t val32)
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{
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oct_write64(csr_addr, (uint64_t) val32);
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}
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#define oct_readint32(a) ((int32_t)oct_read32((a)))
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/*
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* octeon_machdep.c
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*
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* Direct to Board Support level.
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*/
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extern void octeon_led_write_char(int char_position, char val);
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extern void octeon_led_write_hexchar(int char_position, char hexval);
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extern void octeon_led_write_hex(uint32_t wl);
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extern void octeon_led_write_string(const char *str);
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extern void octeon_reset(void);
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extern void octeon_led_write_char0(char val);
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extern void octeon_led_run_wheel(int *pos, int led_position);
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extern void octeon_debug_symbol(void);
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extern void octeon_ciu_reset(void);
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extern int octeon_is_simulation(void);
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#endif /* LOCORE */
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/*
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* EBT3000 LED Unit
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*/
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#define OCTEON_CHAR_LED_BASE_ADDR (0x1d020000 | (0x1ffffffffull << 31))
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/*
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* Default FLASH device (physical) base address
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*/
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#define OCTEON_FLASH_BASE_ADDR (0x1d040000ull)
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#endif /* !OCTEON_PCMAP_REGS_H__ */
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