9a8f61fb5b
X1000 systems on chips. Imgtec CI20 and Ingenic CANNA boards supported. Submitted by: Alexander Kabaev <kan@FreeBSD.org> Reviewed by: Ruslan Bukin <br@FreeBSD.org> Sponsored by: DARPA, AFRL
183 lines
4.2 KiB
C
183 lines
4.2 KiB
C
/*-
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* Copyright (c) 2015 Alexander Kabaev <kan@FreeBSD.org>
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* Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/smp.h>
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#include <sys/systm.h>
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#include <machine/cpufunc.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/smp.h>
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#include <mips/ingenic/jz4780_regs.h>
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#include <mips/ingenic/jz4780_cpuregs.h>
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void jz4780_mpentry(void);
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#define JZ4780_MAXCPU 2
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void
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platform_ipi_send(int cpuid)
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{
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if (cpuid == 0)
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mips_wr_xburst_mbox0(1);
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else
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mips_wr_xburst_mbox1(1);
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}
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void
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platform_ipi_clear(void)
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{
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int cpuid = PCPU_GET(cpuid);
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uint32_t action;
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action = (cpuid == 0) ? mips_rd_xburst_mbox0() : mips_rd_xburst_mbox1();
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KASSERT(action == 1, ("CPU %d: unexpected IPIs: %#x", cpuid, action));
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mips_wr_xburst_core_sts(~(JZ_CORESTS_MIRQ0P << cpuid));
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}
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int
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platform_processor_id(void)
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{
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return (mips_rd_ebase() & 7);
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}
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int
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platform_ipi_hardintr_num(void)
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{
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return (1);
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}
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int
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platform_ipi_softintr_num(void)
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{
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return (-1);
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}
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void
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platform_init_ap(int cpuid)
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{
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unsigned reg;
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/*
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* Clear any pending IPIs.
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*/
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mips_wr_xburst_core_sts(~(JZ_CORESTS_MIRQ0P << cpuid));
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/* Allow IPI mbox for this core */
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reg = mips_rd_xburst_reim();
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reg |= (JZ_REIM_MIRQ0M << cpuid);
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mips_wr_xburst_reim(reg);
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/*
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* Unmask the ipi interrupts.
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*/
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reg = hard_int_mask(platform_ipi_hardintr_num());
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set_intr_mask(reg);
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}
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void
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platform_cpu_mask(cpuset_t *mask)
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{
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uint32_t i, m;
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CPU_ZERO(mask);
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for (i = 0, m = 1 ; i < JZ4780_MAXCPU; i++, m <<= 1)
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CPU_SET(i, mask);
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}
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struct cpu_group *
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platform_smp_topo(void)
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{
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return (smp_topo_none());
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}
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static void
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jz4780_core_powerup(void)
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{
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uint32_t reg;
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reg = readreg(JZ_CGU_BASE + JZ_LPCR);
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reg &= ~LPCR_PD_SCPU;
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writereg(JZ_CGU_BASE + JZ_LPCR, reg);
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do {
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reg = readreg(JZ_CGU_BASE + JZ_LPCR);
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} while ((reg & LPCR_SCPUS) != 0);
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}
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/*
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* Spin up the second code. The code is roughly modeled after
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* similar routine in Linux.
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*/
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int
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platform_start_ap(int cpuid)
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{
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uint32_t reg, addr;
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if (cpuid >= JZ4780_MAXCPU)
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return (EINVAL);
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/* Figure out address of mpentry in KSEG1 */
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addr = MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(jz4780_mpentry));
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KASSERT((addr & ~JZ_REIM_ENTRY_MASK) == 0,
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("Unaligned mpentry"));
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/* Configure core alternative entry point */
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reg = mips_rd_xburst_reim();
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reg &= ~JZ_REIM_ENTRY_MASK;
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reg |= addr & JZ_REIM_ENTRY_MASK;
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/* Allow this core to get IPIs from one being started */
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reg |= JZ_REIM_MIRQ0M;
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mips_wr_xburst_reim(reg);
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/* Force core into reset and enable use of alternate entry point */
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reg = mips_rd_xburst_core_ctl();
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reg |= (JZ_CORECTL_SWRST0 << cpuid) | (JZ_CORECTL_RPC0 << cpuid);
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mips_wr_xburst_core_ctl(reg);
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/* Power the core up */
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jz4780_core_powerup();
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/* Take the core out of reset */
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reg &= ~(JZ_CORECTL_SWRST0 << cpuid);
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mips_wr_xburst_core_ctl(reg);
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return (0);
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}
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