9a8f61fb5b
X1000 systems on chips. Imgtec CI20 and Ingenic CANNA boards supported. Submitted by: Alexander Kabaev <kan@FreeBSD.org> Reviewed by: Ruslan Bukin <br@FreeBSD.org> Sponsored by: DARPA, AFRL
63 lines
2.0 KiB
ArmAsm
63 lines
2.0 KiB
ArmAsm
/*-
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* Copyright (c) 2015 Alexander Kabaev
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <machine/asm.h>
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#include <machine/cpu.h>
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#include <machine/cpuregs.h>
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#include <machine/cache_r4k.h>
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#include "assym.s"
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#define CACHE_SIZE (32 * 1024)
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#define CACHE_LINESIZE 32
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.text
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.set noat
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.set noreorder
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.section .text.mpentry_jz4780
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.balign 0x10000
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GLOBAL(jz4780_mpentry)
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/* Initialize caches */
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li t0, MIPS_KSEG0_START
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ori t1, t0, CACHE_SIZE
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mtc0 zero, MIPS_COP_0_TAG_LO
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COP0_SYNC
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1: cache CACHEOP_R4K_INDEX_STORE_TAG | CACHE_R4K_I, 0(t0)
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cache CACHEOP_R4K_INDEX_STORE_TAG | CACHE_R4K_D, 0(t0)
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bne t0, t1, 1b
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addiu t0, t0, CACHE_LINESIZE
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/* Set TLB page mask */
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mtc0 zero, MIPS_COP_0_TLB_PG_MASK
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COP0_SYNC
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j mpentry
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nop
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