6d2d7b8c0d
already supported nested PICs, but was limited to having a nested
AT-PIC only. With G5 support the need for nested OpenPIC controllers
needed to be added. This was done the wrong way and broke the MPC8555
eval system in the process.
OFW, as well as FDT, describe the interrupt routing in terms of a
controller and an interrupt pin on it. This needs to be mapped to a
flat and global resource: the IRQ. The IRQ is the same as the PCI
intline and as such needs to be representable in 8 bits. Secondly,
ISA support pretty much dictates that IRQ 0-15 should be reserved
for ISA interrupts, because of the internal workins of south bridges.
Both were broken.
This change reverts revision 209298 for a big part and re-implements
it simpler. In particular:
o The id() method of the PIC I/F is removed again. It's not needed.
o The openpic_attach() function has been changed to take the OFW
or FDT phandle of the controller as a second argument. All bus
attachments that previously used openpic_attach() as the attach
method of the device I/F now implement as bus-specific method
and pass the phandle_t to the renamed openpic_attach().
o Change powerpc_register_pic() to take a few more arguments. In
particular:
- Pass the number of IPIs specificly. The number of IRQs carved
out for a PIC is the sum of the number of int. pins and IPIs.
- Pass a flag indicating whether the PIC is an AT-PIC or not.
This tells the interrupt framework whether to assign IRQ 0-15
or some other range.
o Until we implement proper multi-pass bus enumeration, we have to
handle the case where we need to map from PIC+pin to IRQ *before*
the PIC gets registered. This is done in a similar way as before,
but rather than carving out 256 IRQs per PIC, we carve out 128
IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case,
but should really be fixed properly using multiple passes.
o Have the interrupt framework set root_pic in most cases and not
put that burden in PIC drivers (for the most part).
o Remove powerpc_ign_lookup() and replace it with powerpc_get_irq().
Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN.
Related to the above, fix the Freescale PCI controller driver, broken
by the FDT code. Besides not attaching properly, bus numbers were
assigned improperly and enumeration was broken in general. This
prevented the AT PIC from being discovered and interrupt routing to
work properly. Consequently, the ata(4) controller stopped functioning.
Fix the driver, and FDT PCI support, enough to get the MPC8555CDS
going again. The FDT PCI code needs a whole lot more work.
No breakages are expected, but lackiong G5 hardware, it's possible
that there are unpleasant side-effects. At least MPC85xx support is
back to where it was 7 months ago -- it's amazing how badly support
can be broken in just 7 months...
Sponsored by: Juniper Networks
244 lines
6.1 KiB
C
244 lines
6.1 KiB
C
/*-
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* Copyright 2010 Nathan Whitehorn
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/platform.h>
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#include "ps3-hvcall.h"
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#include "pic_if.h"
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static void ps3pic_identify(driver_t *driver, device_t parent);
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static int ps3pic_probe(device_t);
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static int ps3pic_attach(device_t);
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static void ps3pic_dispatch(device_t, struct trapframe *);
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static void ps3pic_enable(device_t, u_int, u_int);
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static void ps3pic_eoi(device_t, u_int);
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static void ps3pic_ipi(device_t, u_int);
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static void ps3pic_mask(device_t, u_int);
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static void ps3pic_unmask(device_t, u_int);
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struct ps3pic_softc {
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uint64_t *bitmap_thread0;
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uint64_t *mask_thread0;
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uint64_t *bitmap_thread1;
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uint64_t *mask_thread1;
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uint64_t sc_ipi_outlet[2];
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int sc_vector[64];
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};
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static device_method_t ps3pic_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, ps3pic_identify),
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DEVMETHOD(device_probe, ps3pic_probe),
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DEVMETHOD(device_attach, ps3pic_attach),
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/* PIC interface */
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DEVMETHOD(pic_dispatch, ps3pic_dispatch),
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DEVMETHOD(pic_enable, ps3pic_enable),
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DEVMETHOD(pic_eoi, ps3pic_eoi),
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DEVMETHOD(pic_ipi, ps3pic_ipi),
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DEVMETHOD(pic_mask, ps3pic_mask),
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DEVMETHOD(pic_unmask, ps3pic_unmask),
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{ 0, 0 },
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};
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static driver_t ps3pic_driver = {
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"ps3pic",
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ps3pic_methods,
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sizeof(struct ps3pic_softc)
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};
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static devclass_t ps3pic_devclass;
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DRIVER_MODULE(ps3pic, nexus, ps3pic_driver, ps3pic_devclass, 0, 0);
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static MALLOC_DEFINE(M_PS3PIC, "ps3pic", "PS3 PIC");
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static void
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ps3pic_identify(driver_t *driver, device_t parent)
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{
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if (strcmp(installed_platform(), "ps3") != 0)
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return;
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if (device_find_child(parent, "ps3pic", -1) == NULL)
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BUS_ADD_CHILD(parent, 0, "ps3pic", 0);
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}
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static int
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ps3pic_probe(device_t dev)
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{
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device_set_desc(dev, "Playstation 3 interrupt controller");
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return (BUS_PROBE_NOWILDCARD);
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}
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static int
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ps3pic_attach(device_t dev)
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{
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struct ps3pic_softc *sc;
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uint64_t ppe;
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int thread;
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sc = device_get_softc(dev);
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sc->bitmap_thread0 = contigmalloc(128 /* 512 bits * 2 */, M_PS3PIC,
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M_NOWAIT | M_ZERO, 0, BUS_SPACE_MAXADDR, 64 /* alignment */,
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PAGE_SIZE /* boundary */);
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sc->mask_thread0 = sc->bitmap_thread0 + 4;
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sc->bitmap_thread1 = sc->bitmap_thread0 + 8;
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sc->mask_thread1 = sc->bitmap_thread0 + 12;
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lv1_get_logical_ppe_id(&ppe);
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thread = 32 - fls(mfctrl());
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lv1_configure_irq_state_bitmap(ppe, thread,
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vtophys(sc->bitmap_thread0));
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#ifdef SMP
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lv1_configure_irq_state_bitmap(ppe, !thread,
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vtophys(sc->bitmap_thread1));
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/* Map both IPIs to the same VIRQ to avoid changes in intr_machdep */
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lv1_construct_event_receive_port(&sc->sc_ipi_outlet[0]);
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lv1_connect_irq_plug_ext(ppe, thread, sc->sc_ipi_outlet[0],
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sc->sc_ipi_outlet[0], 0);
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lv1_construct_event_receive_port(&sc->sc_ipi_outlet[1]);
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lv1_connect_irq_plug_ext(ppe, !thread, sc->sc_ipi_outlet[0],
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sc->sc_ipi_outlet[1], 0);
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#endif
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powerpc_register_pic(dev, 0, sc->sc_ipi_outlet[0], 1, FALSE);
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return (0);
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}
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/*
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* PIC I/F methods.
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*/
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static void
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ps3pic_dispatch(device_t dev, struct trapframe *tf)
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{
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uint64_t bitmap, mask;
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int irq;
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struct ps3pic_softc *sc;
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sc = device_get_softc(dev);
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if (PCPU_GET(cpuid) == 0) {
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bitmap = sc->bitmap_thread0[0];
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mask = sc->mask_thread0[0];
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} else {
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bitmap = sc->bitmap_thread1[0];
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mask = sc->mask_thread1[0];
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}
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while ((irq = ffsl(bitmap & mask) - 1) != -1) {
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bitmap &= ~(1UL << irq);
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powerpc_dispatch_intr(sc->sc_vector[63 - irq], tf);
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}
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}
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static void
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ps3pic_enable(device_t dev, u_int irq, u_int vector)
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{
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struct ps3pic_softc *sc;
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sc = device_get_softc(dev);
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sc->sc_vector[irq] = vector;
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ps3pic_unmask(dev, irq);
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}
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static void
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ps3pic_eoi(device_t dev, u_int irq)
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{
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uint64_t ppe;
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int thread;
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lv1_get_logical_ppe_id(&ppe);
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thread = 32 - fls(mfctrl());
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lv1_end_of_interrupt_ext(ppe, thread, irq);
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}
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static void
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ps3pic_ipi(device_t dev, u_int cpu)
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{
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struct ps3pic_softc *sc;
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sc = device_get_softc(dev);
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lv1_send_event_locally(sc->sc_ipi_outlet[cpu]);
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}
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static void
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ps3pic_mask(device_t dev, u_int irq)
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{
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struct ps3pic_softc *sc;
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uint64_t ppe;
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sc = device_get_softc(dev);
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/* Do not mask IPIs! */
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if (irq == sc->sc_ipi_outlet[0])
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return;
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sc->mask_thread0[0] &= ~(1UL << (63 - irq));
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sc->mask_thread1[0] &= ~(1UL << (63 - irq));
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lv1_get_logical_ppe_id(&ppe);
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lv1_did_update_interrupt_mask(ppe, 0);
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lv1_did_update_interrupt_mask(ppe, 1);
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}
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static void
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ps3pic_unmask(device_t dev, u_int irq)
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{
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struct ps3pic_softc *sc;
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uint64_t ppe;
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sc = device_get_softc(dev);
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sc->mask_thread0[0] |= (1UL << (63 - irq));
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sc->mask_thread1[0] |= (1UL << (63 - irq));
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lv1_get_logical_ppe_id(&ppe);
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lv1_did_update_interrupt_mask(ppe, 0);
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lv1_did_update_interrupt_mask(ppe, 1);
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}
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