c9ea007c3b
o Parse the ACPI DSD (Device Specific Data) graph property and record device connections. o Split-out FDT support to a separate file. o Get the corresponding (FDT/ACPI) Coresight platform data in the device drivers. Sponsored by: DARPA, AFRL
185 lines
11 KiB
C
185 lines
11 KiB
C
/*-
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* Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by BAE Systems, the University of Cambridge
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* Computer Laboratory, and Memorial University under DARPA/AFRL contract
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* FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
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* (TC) research program.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ARM64_CORESIGHT_ETM4X_H_
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#define _ARM64_CORESIGHT_ETM4X_H_
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#define TRCPRGCTLR 0x004 /* Trace Programming Control Register */
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#define TRCPRGCTLR_EN (1 << 0) /* Trace unit enable bit */
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#define TRCPROCSELR 0x008 /* Trace PE Select Control Register */
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#define TRCSTATR 0x00C /* Trace Trace Status Register */
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#define TRCSTATR_PMSTABLE (1 << 1) /* The programmers' model is stable. */
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#define TRCSTATR_IDLE (1 << 0) /* The trace unit is idle. */
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#define TRCCONFIGR 0x010 /* Trace Trace Configuration Register */
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#define TRCCONFIGR_DV (1 << 17) /* Data value tracing is enabled when INSTP0 is not 0b00 */
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#define TRCCONFIGR_DA (1 << 16) /* Data address tracing is enabled when INSTP0 is not 0b00. */
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#define TRCCONFIGR_VMIDOPT (1 << 15) /* Control bit to configure the Virtual context identifier value */
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#define TRCCONFIGR_QE_S 13 /* Q element enable field */
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#define TRCCONFIGR_QE_M (0x3 << TRCCONFIGR_QE_S)
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#define TRCCONFIGR_RS (1 << 12) /* Return stack enable bit */
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#define TRCCONFIGR_TS (1 << 11) /* Global timestamp tracing is enabled. */
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#define TRCCONFIGR_COND_S 8 /* Conditional instruction tracing bit. */
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#define TRCCONFIGR_COND_M (0x7 << TRCCONFIGR_COND_S)
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#define TRCCONFIGR_COND_DIS 0
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#define TRCCONFIGR_COND_LDR (1 << TRCCONFIGR_COND_S) /* Conditional load instructions are traced. */
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#define TRCCONFIGR_COND_STR (2 << TRCCONFIGR_COND_S) /* Conditional store instructions are traced. */
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#define TRCCONFIGR_COND_LDRSTR (3 << TRCCONFIGR_COND_S) /* Conditional load and store instructions are traced. */
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#define TRCCONFIGR_COND_ALL (7 << TRCCONFIGR_COND_S) /* All conditional instructions are traced. */
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#define TRCCONFIGR_VMID (1 << 7) /* Virtual context identifier tracing is enabled. */
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#define TRCCONFIGR_CID (1 << 6) /* Context ID tracing is enabled. */
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#define TRCCONFIGR_CCI (1 << 4) /* Cycle counting in the instruction trace is enabled. */
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#define TRCCONFIGR_BB (1 << 3) /* Branch broadcast mode is enabled. */
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#define TRCCONFIGR_INSTP0_S 1 /* Instruction P0 field. */
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#define TRCCONFIGR_INSTP0_M (0x3 << TRCCONFIGR_INSTP0_S)
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#define TRCCONFIGR_INSTP0_NONE 0 /* Do not trace load and store instructions as P0 instructions. */
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#define TRCCONFIGR_INSTP0_LDR (1 << TRCCONFIGR_INSTP0_S) /* Trace load instructions as P0 instructions. */
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#define TRCCONFIGR_INSTP0_STR (2 << TRCCONFIGR_INSTP0_S) /* Trace store instructions as P0 instructions. */
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#define TRCCONFIGR_INSTP0_LDRSTR (3 << TRCCONFIGR_INSTP0_S) /* Trace load and store instructions as P0 instr. */
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#define TRCAUXCTLR 0x018 /* Trace Auxiliary Control Register */
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#define TRCEVENTCTL0R 0x020 /* Trace Event Control 0 Register */
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#define TRCEVENTCTL1R 0x024 /* Trace Event Control 1 Register */
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#define TRCSTALLCTLR 0x02C /* Trace Stall Control Register */
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#define TRCTSCTLR 0x030 /* Trace Global Timestamp Control Register */
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#define TRCSYNCPR 0x034 /* Trace Synchronization Period Register */
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#define TRCSYNCPR_PERIOD_S 0
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#define TRCSYNCPR_PERIOD_M 0x1f
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#define TRCSYNCPR_1K (10 << TRCSYNCPR_PERIOD_S)
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#define TRCSYNCPR_2K (11 << TRCSYNCPR_PERIOD_S)
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#define TRCSYNCPR_4K (12 << TRCSYNCPR_PERIOD_S)
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#define TRCCCCTLR 0x038 /* Trace Cycle Count Control Register */
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#define TRCBBCTLR 0x03C /* Trace Branch Broadcast Control Register */
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#define TRCTRACEIDR 0x040 /* Trace Trace ID Register */
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#define TRCQCTLR 0x044 /* Trace Q Element Control Register */
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#define TRCQCTLR_MODE_INC (1 << 8) /* Include mode. */
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#define TRCVICTLR 0x080 /* Trace ViewInst Main Control Register */
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#define TRCVICTLR_SSSTATUS (1 << 9) /* The start/stop logic is in the started state. */
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#define TRCVICTLR_EXLEVEL_NS_S 20
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#define TRCVICTLR_EXLEVEL_NS_M (0xf << TRCVICTLR_EXLEVEL_NS_S)
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#define TRCVICTLR_EXLEVEL_NS(n) (0x1 << ((n) + TRCVICTLR_EXLEVEL_NS_S))
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#define TRCVICTLR_EXLEVEL_S_S 16
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#define TRCVICTLR_EXLEVEL_S_M (0xf << TRCVICTLR_EXLEVEL_S_S)
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#define TRCVICTLR_EXLEVEL_S(n) (0x1 << ((n) + TRCVICTLR_EXLEVEL_S_S))
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#define EVENT_SEL_S 0
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#define EVENT_SEL_M (0x1f << EVENT_SEL_S)
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#define TRCVIIECTLR 0x084 /* Trace ViewInst Include/Exclude Control Register */
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#define TRCVIIECTLR_INCLUDE_S 0
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#define TRCVISSCTLR 0x088 /* Trace ViewInst Start/Stop Control Register */
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#define TRCVIPCSSCTLR 0x08C /* Trace ViewInst Start/Stop PE Comparator Control Register */
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#define TRCVDCTLR 0x0A0 /* Trace ViewData Main Control Register */
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#define TRCVDCTLR_TRCEXDATA (1 << 12) /* Exception and exception return data transfers are traced */
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#define TRCVDCTLR_TBI (1 << 11) /* The trace unit assigns bits[63:56] to have the same value as bits[63:56] of the data address. */
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#define TRCVDCTLR_PCREL (1 << 10) /* The trace unit does not trace the address or value portions of PC-relative transfers. */
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#define TRCVDCTLR_SPREL_S 8
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#define TRCVDCTLR_SPREL_M (0x3 << TRCVDCTLR_SPREL_S)
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#define TRCVDCTLR_EVENT_S 0
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#define TRCVDCTLR_EVENT_M (0xff << TRCVDCTLR_EVENT_S)
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#define TRCVDSACCTLR 0x0A4 /* Trace ViewData Include/Exclude Single Address Comparator Control Register */
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#define TRCVDARCCTLR 0x0A8 /* Trace ViewData Include/Exclude Address Range Comparator Control Register */
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#define TRCSEQEVR(n) (0x100 + (n) * 0x4) /* Trace Sequencer State Transition Control Register [n=0-2] */
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#define TRCSEQRSTEVR 0x118 /* Trace Sequencer Reset Control Register */
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#define TRCSEQSTR 0x11C /* Trace Sequencer State Register */
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#define TRCEXTINSELR 0x120 /* Trace External Input Select Register */
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#define TRCCNTRLDVR(n) (0x140 + (n) * 0x4) /* 32 Trace Counter Reload Value Register [n=0-3] */
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#define TRCCNTCTLR(n) (0x150 + (n) * 0x4) /* 32 Trace Counter Control Register [n=0-3] */
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#define TRCCNTVR(n) (0x160 + (n) * 0x4) /* 32 Trace Counter Value Register [n=0-3] */
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#define TRCIMSPEC(n) (0x1C0 + (n) * 0x4) /* Trace IMPLEMENTATION DEFINED register [n=0-7] */
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#define TRCIDR0(n) (0x1E0 + 0x4 * (n))
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#define TRCIDR8(n) (0x180 + 0x4 * (n))
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#define TRCIDR(n) ((n > 7) ? TRCIDR8(n) : TRCIDR0(n))
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#define TRCIDR1_TRCARCHMAJ_S 8
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#define TRCIDR1_TRCARCHMAJ_M (0xf << TRCIDR1_TRCARCHMAJ_S)
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#define TRCIDR1_TRCARCHMIN_S 4
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#define TRCIDR1_TRCARCHMIN_M (0xf << TRCIDR1_TRCARCHMIN_S)
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#define TRCRSCTLR(n) (0x200 + (n) * 0x4) /* Trace Resource Selection Control Register [n=2-31] */
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#define TRCSSCCR(n) (0x280 + (n) * 0x4) /* Trace Single-shot Comparator Control Register [n=0-7] */
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#define TRCSSCSR(n) (0x2A0 + (n) * 0x4) /* Trace Single-shot Comparator Status Register [n=0-7] */
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#define TRCSSPCICR(n) (0x2C0 + (n) * 0x4) /* Trace Single-shot PE Comparator Input Control [n=0-7] */
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#define TRCOSLAR 0x300 /* Management OS Lock Access Register */
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#define TRCOSLSR 0x304 /* Management OS Lock Status Register */
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#define TRCPDCR 0x310 /* Management PowerDown Control Register */
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#define TRCPDSR 0x314 /* Management PowerDown Status Register */
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#define TRCACVR(n) (0x400 + (n) * 0x8) /* Trace Address Comparator Value Register [n=0-15] */
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#define TRCACATR(n) (0x480 + (n) * 0x8) /* Trace Address Comparator Access Type Register [n=0-15] */
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#define TRCACATR_DTBM (1 << 21)
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#define TRCACATR_DATARANGE (1 << 20)
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#define TRCACATR_DATASIZE_S 18
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#define TRCACATR_DATASIZE_M (0x3 << TRCACATR_DATASIZE_S)
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#define TRCACATR_DATASIZE_B (0x0 << TRCACATR_DATASIZE_S)
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#define TRCACATR_DATASIZE_HW (0x1 << TRCACATR_DATASIZE_S)
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#define TRCACATR_DATASIZE_W (0x2 << TRCACATR_DATASIZE_S)
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#define TRCACATR_DATASIZE_DW (0x3 << TRCACATR_DATASIZE_S)
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#define TRCACATR_DATAMATCH_S 16
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#define TRCACATR_DATAMATCH_M (0x3 << TRCACATR_DATAMATCH_S)
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#define TRCACATR_EXLEVEL_S_S 8
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#define TRCACATR_EXLEVEL_S_M (0xf << TRCACATR_EXLEVEL_S_S)
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#define TRCACATR_EXLEVEL_S(n) (0x1 << ((n) + TRCACATR_EXLEVEL_S_S))
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#define TRCACATR_EXLEVEL_NS_S 12
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#define TRCACATR_EXLEVEL_NS_M (0xf << TRCACATR_EXLEVEL_NS_S)
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#define TRCACATR_EXLEVEL_NS(n) (0x1 << ((n) + TRCACATR_EXLEVEL_NS_S))
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#define TRCDVCVR(n) (0x500 + (n) * 0x8) /* Trace Data Value Comparator Value Register [n=0-7] */
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#define TRCDVCMR(n) (0x580 + (n) * 0x8) /* Trace Data Value Comparator Mask Register [n=0-7] */
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#define TRCCIDCVR(n) (0x600 + (n) * 0x8) /* Trace Context ID Comparator Value Register [n=0-7] */
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#define TRCVMIDCVR(n) (0x640 + (n) * 0x8) /* Trace Virtual context identifier Comparator Value [n=0-7] */
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#define TRCCIDCCTLR0 0x680 /* Trace Context ID Comparator Control Register 0 */
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#define TRCCIDCCTLR1 0x684 /* Trace Context ID Comparator Control Register 1 */
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#define TRCVMIDCCTLR0 0x688 /* Trace Virtual context identifier Comparator Control Register 0 */
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#define TRCVMIDCCTLR1 0x68C /* Trace Virtual context identifier Comparator Control Register 1 */
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#define TRCITCTRL 0xF00 /* Management Integration Mode Control register */
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#define TRCCLAIMSET 0xFA0 /* Trace Claim Tag Set register */
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#define TRCCLAIMCLR 0xFA4 /* Trace Claim Tag Clear register */
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#define TRCDEVAFF0 0xFA8 /* Management Device Affinity register 0 */
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#define TRCDEVAFF1 0xFAC /* Management Device Affinity register 1 */
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#define TRCLAR 0xFB0 /* Management Software Lock Access Register */
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#define TRCLSR 0xFB4 /* Management Software Lock Status Register */
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#define TRCAUTHSTATUS 0xFB8 /* Management Authentication Status register */
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#define TRCDEVARCH 0xFBC /* Management Device Architecture register */
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#define TRCDEVID 0xFC8 /* Management Device ID register */
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#define TRCDEVTYPE 0xFCC /* Management Device Type register */
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#define TRCPIDR4 0xFD0 /* Management Peripheral ID4 Register */
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#define TRCPIDR(n) (0xFE0 + (n) * 0x4) /* Management Peripheral IDn Register [n=0-3] */
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#define TRCPIDR567(n) (0xFD4 + ((n) - 5) * 0x4) /* Management Peripheral ID5 to Peripheral ID7 Registers */
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#define TRCCIDR(n) (0xFF0 + (n) * 0x4) /* Management Component IDn Register [n=0-4] */
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DECLARE_CLASS(etm_driver);
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struct etm_softc {
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struct resource *res;
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struct coresight_platform_data *pdata;
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};
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int etm_attach(device_t dev);
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#endif /* !_ARM64_CORESIGHT_ETM4X_H_ */
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