9aafc7c052
This is a lock-based emulation of 64-bit atomics for kernel use, split off from an earlier patch by jhibbits. This is needed to unblock future improvements that reduce the need for locking on 64-bit platforms by using atomic updates. The implementation allows for future integration with userland atomic64, but as that implies going through sysarch for every use, the current status quo of userland doing its own locking may be for the best. Submitted by: jhibbits (original patch), kevans (mips bits) Reviewed by: jhibbits, jeff, kevans Differential Revision: https://reviews.freebsd.org/D22976
852 lines
25 KiB
C
852 lines
25 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: src/sys/alpha/include/atomic.h,v 1.21.2.3 2005/10/06 18:12:05 jhb
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ATOMIC_H_
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#define _MACHINE_ATOMIC_H_
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#ifndef _SYS_CDEFS_H_
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#error this file needs sys/cdefs.h as a prerequisite
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#endif
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#include <sys/atomic_common.h>
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#if !defined(__mips_n64) && !defined(__mips_n32)
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#include <sys/_atomic64e.h>
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#endif
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/*
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* Note: All the 64-bit atomic operations are only atomic when running
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* in 64-bit mode. It is assumed that code compiled for n32 and n64
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* fits into this definition and no further safeties are needed.
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*
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* It is also assumed that the add, subtract and other arithmetic is
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* done on numbers not pointers. The special rules for n32 pointers
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* do not have atomic operations defined for them, but generally shouldn't
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* need atomic operations.
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*/
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#ifndef __MIPS_PLATFORM_SYNC_NOPS
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#define __MIPS_PLATFORM_SYNC_NOPS ""
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#endif
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static __inline void
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mips_sync(void)
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{
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__asm __volatile (".set noreorder\n"
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"\tsync\n"
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__MIPS_PLATFORM_SYNC_NOPS
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".set reorder\n"
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: : : "memory");
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}
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#define mb() mips_sync()
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#define wmb() mips_sync()
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#define rmb() mips_sync()
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/*
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* Various simple arithmetic on memory which is atomic in the presence
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* of interrupts and SMP safe.
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*/
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void atomic_set_8(__volatile uint8_t *, uint8_t);
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void atomic_clear_8(__volatile uint8_t *, uint8_t);
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void atomic_add_8(__volatile uint8_t *, uint8_t);
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void atomic_subtract_8(__volatile uint8_t *, uint8_t);
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void atomic_set_16(__volatile uint16_t *, uint16_t);
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void atomic_clear_16(__volatile uint16_t *, uint16_t);
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void atomic_add_16(__volatile uint16_t *, uint16_t);
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void atomic_subtract_16(__volatile uint16_t *, uint16_t);
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static __inline int atomic_cmpset_8(__volatile uint8_t *, uint8_t, uint8_t);
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static __inline int atomic_fcmpset_8(__volatile uint8_t *, uint8_t *, uint8_t);
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static __inline int atomic_cmpset_16(__volatile uint16_t *, uint16_t, uint16_t);
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static __inline int atomic_fcmpset_16(__volatile uint16_t *, uint16_t *, uint16_t);
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static __inline void
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atomic_set_32(__volatile uint32_t *p, uint32_t v)
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{
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uint32_t temp;
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__asm __volatile (
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"1:\tll %0, %3\n\t" /* load old value */
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"or %0, %2, %0\n\t" /* calculate new value */
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"sc %0, %1\n\t" /* attempt to store */
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"beqz %0, 1b\n\t" /* spin if failed */
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: "=&r" (temp), "=m" (*p)
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: "r" (v), "m" (*p)
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: "memory");
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}
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static __inline void
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atomic_clear_32(__volatile uint32_t *p, uint32_t v)
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{
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uint32_t temp;
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v = ~v;
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__asm __volatile (
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"1:\tll %0, %3\n\t" /* load old value */
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"and %0, %2, %0\n\t" /* calculate new value */
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"sc %0, %1\n\t" /* attempt to store */
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"beqz %0, 1b\n\t" /* spin if failed */
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: "=&r" (temp), "=m" (*p)
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: "r" (v), "m" (*p)
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: "memory");
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}
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static __inline void
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atomic_add_32(__volatile uint32_t *p, uint32_t v)
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{
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uint32_t temp;
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__asm __volatile (
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"1:\tll %0, %3\n\t" /* load old value */
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"addu %0, %2, %0\n\t" /* calculate new value */
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"sc %0, %1\n\t" /* attempt to store */
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"beqz %0, 1b\n\t" /* spin if failed */
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: "=&r" (temp), "=m" (*p)
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: "r" (v), "m" (*p)
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: "memory");
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}
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static __inline void
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atomic_subtract_32(__volatile uint32_t *p, uint32_t v)
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{
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uint32_t temp;
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__asm __volatile (
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"1:\tll %0, %3\n\t" /* load old value */
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"subu %0, %2\n\t" /* calculate new value */
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"sc %0, %1\n\t" /* attempt to store */
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"beqz %0, 1b\n\t" /* spin if failed */
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: "=&r" (temp), "=m" (*p)
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: "r" (v), "m" (*p)
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: "memory");
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}
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static __inline uint32_t
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atomic_readandclear_32(__volatile uint32_t *addr)
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{
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uint32_t result,temp;
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__asm __volatile (
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"1:\tll %0,%3\n\t" /* load current value, asserting lock */
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"li %1,0\n\t" /* value to store */
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"sc %1,%2\n\t" /* attempt to store */
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"beqz %1, 1b\n\t" /* if the store failed, spin */
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: "=&r"(result), "=&r"(temp), "=m" (*addr)
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: "m" (*addr)
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: "memory");
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return result;
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}
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static __inline uint32_t
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atomic_readandset_32(__volatile uint32_t *addr, uint32_t value)
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{
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uint32_t result,temp;
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__asm __volatile (
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"1:\tll %0,%3\n\t" /* load current value, asserting lock */
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"or %1,$0,%4\n\t"
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"sc %1,%2\n\t" /* attempt to store */
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"beqz %1, 1b\n\t" /* if the store failed, spin */
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: "=&r"(result), "=&r"(temp), "=m" (*addr)
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: "m" (*addr), "r" (value)
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: "memory");
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return result;
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}
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#if defined(__mips_n64) || defined(__mips_n32)
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static __inline void
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atomic_set_64(__volatile uint64_t *p, uint64_t v)
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{
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uint64_t temp;
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__asm __volatile (
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"1:\n\t"
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"lld %0, %3\n\t" /* load old value */
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"or %0, %2, %0\n\t" /* calculate new value */
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"scd %0, %1\n\t" /* attempt to store */
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"beqz %0, 1b\n\t" /* spin if failed */
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: "=&r" (temp), "=m" (*p)
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: "r" (v), "m" (*p)
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: "memory");
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}
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static __inline void
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atomic_clear_64(__volatile uint64_t *p, uint64_t v)
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{
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uint64_t temp;
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v = ~v;
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__asm __volatile (
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"1:\n\t"
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"lld %0, %3\n\t" /* load old value */
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"and %0, %2, %0\n\t" /* calculate new value */
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"scd %0, %1\n\t" /* attempt to store */
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"beqz %0, 1b\n\t" /* spin if failed */
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: "=&r" (temp), "=m" (*p)
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: "r" (v), "m" (*p)
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: "memory");
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}
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static __inline void
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atomic_add_64(__volatile uint64_t *p, uint64_t v)
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{
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uint64_t temp;
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__asm __volatile (
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"1:\n\t"
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"lld %0, %3\n\t" /* load old value */
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"daddu %0, %2, %0\n\t" /* calculate new value */
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"scd %0, %1\n\t" /* attempt to store */
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"beqz %0, 1b\n\t" /* spin if failed */
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: "=&r" (temp), "=m" (*p)
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: "r" (v), "m" (*p)
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: "memory");
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}
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static __inline void
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atomic_subtract_64(__volatile uint64_t *p, uint64_t v)
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{
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uint64_t temp;
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__asm __volatile (
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"1:\n\t"
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"lld %0, %3\n\t" /* load old value */
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"dsubu %0, %2\n\t" /* calculate new value */
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"scd %0, %1\n\t" /* attempt to store */
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"beqz %0, 1b\n\t" /* spin if failed */
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: "=&r" (temp), "=m" (*p)
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: "r" (v), "m" (*p)
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: "memory");
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}
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static __inline uint64_t
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atomic_readandclear_64(__volatile uint64_t *addr)
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{
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uint64_t result,temp;
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__asm __volatile (
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"1:\n\t"
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"lld %0, %3\n\t" /* load old value */
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"li %1, 0\n\t" /* value to store */
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"scd %1, %2\n\t" /* attempt to store */
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"beqz %1, 1b\n\t" /* if the store failed, spin */
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: "=&r"(result), "=&r"(temp), "=m" (*addr)
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: "m" (*addr)
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: "memory");
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return result;
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}
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static __inline uint64_t
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atomic_readandset_64(__volatile uint64_t *addr, uint64_t value)
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{
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uint64_t result,temp;
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__asm __volatile (
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"1:\n\t"
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"lld %0,%3\n\t" /* Load old value*/
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"or %1,$0,%4\n\t"
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"scd %1,%2\n\t" /* attempt to store */
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"beqz %1, 1b\n\t" /* if the store failed, spin */
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: "=&r"(result), "=&r"(temp), "=m" (*addr)
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: "m" (*addr), "r" (value)
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: "memory");
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return result;
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}
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#endif
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#define ATOMIC_ACQ_REL(NAME, WIDTH) \
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static __inline void \
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atomic_##NAME##_acq_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
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{ \
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atomic_##NAME##_##WIDTH(p, v); \
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mips_sync(); \
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} \
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\
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static __inline void \
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atomic_##NAME##_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
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{ \
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mips_sync(); \
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atomic_##NAME##_##WIDTH(p, v); \
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}
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/* Variants of simple arithmetic with memory barriers. */
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ATOMIC_ACQ_REL(set, 8)
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ATOMIC_ACQ_REL(clear, 8)
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ATOMIC_ACQ_REL(add, 8)
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ATOMIC_ACQ_REL(subtract, 8)
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ATOMIC_ACQ_REL(set, 16)
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ATOMIC_ACQ_REL(clear, 16)
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ATOMIC_ACQ_REL(add, 16)
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ATOMIC_ACQ_REL(subtract, 16)
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ATOMIC_ACQ_REL(set, 32)
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ATOMIC_ACQ_REL(clear, 32)
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ATOMIC_ACQ_REL(add, 32)
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ATOMIC_ACQ_REL(subtract, 32)
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#if defined(__mips_n64) || defined(__mips_n32)
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ATOMIC_ACQ_REL(set, 64)
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ATOMIC_ACQ_REL(clear, 64)
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ATOMIC_ACQ_REL(add, 64)
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ATOMIC_ACQ_REL(subtract, 64)
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#endif
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#undef ATOMIC_ACQ_REL
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/*
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* We assume that a = b will do atomic loads and stores.
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*/
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#define ATOMIC_STORE_LOAD(WIDTH) \
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static __inline uint##WIDTH##_t \
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atomic_load_acq_##WIDTH(__volatile uint##WIDTH##_t *p) \
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{ \
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uint##WIDTH##_t v; \
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\
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v = *p; \
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mips_sync(); \
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return (v); \
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} \
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\
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static __inline void \
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atomic_store_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
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{ \
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mips_sync(); \
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*p = v; \
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}
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ATOMIC_STORE_LOAD(32)
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#if defined(__mips_n64) || defined(__mips_n32)
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ATOMIC_STORE_LOAD(64)
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#endif
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#undef ATOMIC_STORE_LOAD
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/*
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* MIPS n32 is not a LP64 API, so atomic_load_64 isn't defined there. Define it
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* here since n32 is an oddball !LP64 but that can do 64-bit atomics.
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*/
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#if defined(__mips_n32)
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#define atomic_load_64 atomic_load_acq_64
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#endif
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/*
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* Atomically compare the value stored at *p with cmpval and if the
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* two values are equal, update the value of *p with newval. Returns
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* zero if the compare failed, nonzero otherwise.
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*/
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static __inline int
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atomic_cmpset_32(__volatile uint32_t *p, uint32_t cmpval, uint32_t newval)
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{
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int ret;
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__asm __volatile (
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"1:\tll %0, %4\n\t" /* load old value */
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"bne %0, %2, 2f\n\t" /* compare */
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"move %0, %3\n\t" /* value to store */
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"sc %0, %1\n\t" /* attempt to store */
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"beqz %0, 1b\n\t" /* if it failed, spin */
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"j 3f\n\t"
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"2:\n\t"
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"li %0, 0\n\t"
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"3:\n"
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: "=&r" (ret), "=m" (*p)
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: "r" (cmpval), "r" (newval), "m" (*p)
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: "memory");
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return ret;
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}
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/*
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* Atomically compare the value stored at *p with cmpval and if the
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* two values are equal, update the value of *p with newval. Returns
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* zero if the compare failed, nonzero otherwise.
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*/
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static __inline int
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atomic_fcmpset_32(__volatile uint32_t *p, uint32_t *cmpval, uint32_t newval)
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{
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int ret;
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/*
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* The following sequence (similar to that in atomic_fcmpset_64) will
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* attempt to update the value of *p with newval if the comparison
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* succeeds. Note that they'll exit regardless of whether the store
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* actually succeeded, leaving *cmpval untouched. This is in line with
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* the documentation of atomic_fcmpset_<type>() in atomic(9) for ll/sc
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* architectures.
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*/
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__asm __volatile (
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"ll %0, %1\n\t" /* load old value */
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"bne %0, %4, 1f\n\t" /* compare */
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"move %0, %3\n\t" /* value to store */
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"sc %0, %1\n\t" /* attempt to store */
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"j 2f\n\t" /* exit regardless of success */
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"nop\n\t" /* avoid delay slot accident */
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"1:\n\t"
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"sw %0, %2\n\t" /* save old value */
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"li %0, 0\n\t"
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"2:\n"
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: "=&r" (ret), "+m" (*p), "=m" (*cmpval)
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: "r" (newval), "r" (*cmpval)
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: "memory");
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return ret;
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}
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#define ATOMIC_CMPSET_ACQ_REL(WIDTH) \
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static __inline int \
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atomic_cmpset_acq_##WIDTH(__volatile uint##WIDTH##_t *p, \
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uint##WIDTH##_t cmpval, uint##WIDTH##_t newval) \
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{ \
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int retval; \
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\
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retval = atomic_cmpset_##WIDTH(p, cmpval, newval); \
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mips_sync(); \
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return (retval); \
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} \
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\
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static __inline int \
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atomic_cmpset_rel_##WIDTH(__volatile uint##WIDTH##_t *p, \
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uint##WIDTH##_t cmpval, uint##WIDTH##_t newval) \
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{ \
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mips_sync(); \
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return (atomic_cmpset_##WIDTH(p, cmpval, newval)); \
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}
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#define ATOMIC_FCMPSET_ACQ_REL(WIDTH) \
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static __inline int \
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atomic_fcmpset_acq_##WIDTH(__volatile uint##WIDTH##_t *p, \
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uint##WIDTH##_t *cmpval, uint##WIDTH##_t newval) \
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{ \
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int retval; \
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\
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retval = atomic_fcmpset_##WIDTH(p, cmpval, newval); \
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mips_sync(); \
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return (retval); \
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} \
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\
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static __inline int \
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atomic_fcmpset_rel_##WIDTH(__volatile uint##WIDTH##_t *p, \
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uint##WIDTH##_t *cmpval, uint##WIDTH##_t newval) \
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{ \
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mips_sync(); \
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|
return (atomic_fcmpset_##WIDTH(p, cmpval, newval)); \
|
|
}
|
|
|
|
/*
|
|
* Atomically compare the value stored at *p with cmpval and if the
|
|
* two values are equal, update the value of *p with newval. Returns
|
|
* zero if the compare failed, nonzero otherwise.
|
|
*/
|
|
ATOMIC_CMPSET_ACQ_REL(8);
|
|
ATOMIC_CMPSET_ACQ_REL(16);
|
|
ATOMIC_CMPSET_ACQ_REL(32);
|
|
ATOMIC_FCMPSET_ACQ_REL(8);
|
|
ATOMIC_FCMPSET_ACQ_REL(16);
|
|
ATOMIC_FCMPSET_ACQ_REL(32);
|
|
|
|
/*
|
|
* Atomically add the value of v to the integer pointed to by p and return
|
|
* the previous value of *p.
|
|
*/
|
|
static __inline uint32_t
|
|
atomic_fetchadd_32(__volatile uint32_t *p, uint32_t v)
|
|
{
|
|
uint32_t value, temp;
|
|
|
|
__asm __volatile (
|
|
"1:\tll %0, %1\n\t" /* load old value */
|
|
"addu %2, %3, %0\n\t" /* calculate new value */
|
|
"sc %2, %1\n\t" /* attempt to store */
|
|
"beqz %2, 1b\n\t" /* spin if failed */
|
|
: "=&r" (value), "=m" (*p), "=&r" (temp)
|
|
: "r" (v), "m" (*p));
|
|
return (value);
|
|
}
|
|
|
|
#if defined(__mips_n64) || defined(__mips_n32)
|
|
/*
|
|
* Atomically compare the value stored at *p with cmpval and if the
|
|
* two values are equal, update the value of *p with newval. Returns
|
|
* zero if the compare failed, nonzero otherwise.
|
|
*/
|
|
static __inline int
|
|
atomic_cmpset_64(__volatile uint64_t *p, uint64_t cmpval, uint64_t newval)
|
|
{
|
|
int ret;
|
|
|
|
__asm __volatile (
|
|
"1:\n\t"
|
|
"lld %0, %4\n\t" /* load old value */
|
|
"bne %0, %2, 2f\n\t" /* compare */
|
|
"move %0, %3\n\t" /* value to store */
|
|
"scd %0, %1\n\t" /* attempt to store */
|
|
"beqz %0, 1b\n\t" /* if it failed, spin */
|
|
"j 3f\n\t"
|
|
"2:\n\t"
|
|
"li %0, 0\n\t"
|
|
"3:\n"
|
|
: "=&r" (ret), "=m" (*p)
|
|
: "r" (cmpval), "r" (newval), "m" (*p)
|
|
: "memory");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static __inline int
|
|
atomic_fcmpset_64(__volatile uint64_t *p, uint64_t *cmpval, uint64_t newval)
|
|
{
|
|
int ret;
|
|
|
|
__asm __volatile (
|
|
"lld %0, %1\n\t" /* load old value */
|
|
"bne %0, %4, 1f\n\t" /* compare */
|
|
"move %0, %3\n\t" /* value to store */
|
|
"scd %0, %1\n\t" /* attempt to store */
|
|
"j 2f\n\t" /* exit regardless of success */
|
|
"nop\n\t" /* avoid delay slot accident */
|
|
"1:\n\t"
|
|
"sd %0, %2\n\t" /* save old value */
|
|
"li %0, 0\n\t"
|
|
"2:\n"
|
|
: "=&r" (ret), "+m" (*p), "=m" (*cmpval)
|
|
: "r" (newval), "r" (*cmpval)
|
|
: "memory");
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Atomically compare the value stored at *p with cmpval and if the
|
|
* two values are equal, update the value of *p with newval. Returns
|
|
* zero if the compare failed, nonzero otherwise.
|
|
*/
|
|
ATOMIC_CMPSET_ACQ_REL(64);
|
|
ATOMIC_FCMPSET_ACQ_REL(64);
|
|
|
|
/*
|
|
* Atomically add the value of v to the integer pointed to by p and return
|
|
* the previous value of *p.
|
|
*/
|
|
static __inline uint64_t
|
|
atomic_fetchadd_64(__volatile uint64_t *p, uint64_t v)
|
|
{
|
|
uint64_t value, temp;
|
|
|
|
__asm __volatile (
|
|
"1:\n\t"
|
|
"lld %0, %1\n\t" /* load old value */
|
|
"daddu %2, %3, %0\n\t" /* calculate new value */
|
|
"scd %2, %1\n\t" /* attempt to store */
|
|
"beqz %2, 1b\n\t" /* spin if failed */
|
|
: "=&r" (value), "=m" (*p), "=&r" (temp)
|
|
: "r" (v), "m" (*p));
|
|
return (value);
|
|
}
|
|
#endif
|
|
|
|
static __inline void
|
|
atomic_thread_fence_acq(void)
|
|
{
|
|
|
|
mips_sync();
|
|
}
|
|
|
|
static __inline void
|
|
atomic_thread_fence_rel(void)
|
|
{
|
|
|
|
mips_sync();
|
|
}
|
|
|
|
static __inline void
|
|
atomic_thread_fence_acq_rel(void)
|
|
{
|
|
|
|
mips_sync();
|
|
}
|
|
|
|
static __inline void
|
|
atomic_thread_fence_seq_cst(void)
|
|
{
|
|
|
|
mips_sync();
|
|
}
|
|
|
|
/* Operations on chars. */
|
|
#define atomic_set_char atomic_set_8
|
|
#define atomic_set_acq_char atomic_set_acq_8
|
|
#define atomic_set_rel_char atomic_set_rel_8
|
|
#define atomic_clear_char atomic_clear_8
|
|
#define atomic_clear_acq_char atomic_clear_acq_8
|
|
#define atomic_clear_rel_char atomic_clear_rel_8
|
|
#define atomic_add_char atomic_add_8
|
|
#define atomic_add_acq_char atomic_add_acq_8
|
|
#define atomic_add_rel_char atomic_add_rel_8
|
|
#define atomic_subtract_char atomic_subtract_8
|
|
#define atomic_subtract_acq_char atomic_subtract_acq_8
|
|
#define atomic_subtract_rel_char atomic_subtract_rel_8
|
|
#define atomic_cmpset_char atomic_cmpset_8
|
|
#define atomic_cmpset_acq_char atomic_cmpset_acq_8
|
|
#define atomic_cmpset_rel_char atomic_cmpset_rel_8
|
|
#define atomic_fcmpset_char atomic_fcmpset_8
|
|
#define atomic_fcmpset_acq_char atomic_fcmpset_acq_8
|
|
#define atomic_fcmpset_rel_char atomic_fcmpset_rel_8
|
|
|
|
/* Operations on shorts. */
|
|
#define atomic_set_short atomic_set_16
|
|
#define atomic_set_acq_short atomic_set_acq_16
|
|
#define atomic_set_rel_short atomic_set_rel_16
|
|
#define atomic_clear_short atomic_clear_16
|
|
#define atomic_clear_acq_short atomic_clear_acq_16
|
|
#define atomic_clear_rel_short atomic_clear_rel_16
|
|
#define atomic_add_short atomic_add_16
|
|
#define atomic_add_acq_short atomic_add_acq_16
|
|
#define atomic_add_rel_short atomic_add_rel_16
|
|
#define atomic_subtract_short atomic_subtract_16
|
|
#define atomic_subtract_acq_short atomic_subtract_acq_16
|
|
#define atomic_subtract_rel_short atomic_subtract_rel_16
|
|
#define atomic_cmpset_short atomic_cmpset_16
|
|
#define atomic_cmpset_acq_short atomic_cmpset_acq_16
|
|
#define atomic_cmpset_rel_short atomic_cmpset_rel_16
|
|
#define atomic_fcmpset_short atomic_fcmpset_16
|
|
#define atomic_fcmpset_acq_short atomic_fcmpset_acq_16
|
|
#define atomic_fcmpset_rel_short atomic_fcmpset_rel_16
|
|
|
|
/* Operations on ints. */
|
|
#define atomic_set_int atomic_set_32
|
|
#define atomic_set_acq_int atomic_set_acq_32
|
|
#define atomic_set_rel_int atomic_set_rel_32
|
|
#define atomic_clear_int atomic_clear_32
|
|
#define atomic_clear_acq_int atomic_clear_acq_32
|
|
#define atomic_clear_rel_int atomic_clear_rel_32
|
|
#define atomic_add_int atomic_add_32
|
|
#define atomic_add_acq_int atomic_add_acq_32
|
|
#define atomic_add_rel_int atomic_add_rel_32
|
|
#define atomic_subtract_int atomic_subtract_32
|
|
#define atomic_subtract_acq_int atomic_subtract_acq_32
|
|
#define atomic_subtract_rel_int atomic_subtract_rel_32
|
|
#define atomic_cmpset_int atomic_cmpset_32
|
|
#define atomic_cmpset_acq_int atomic_cmpset_acq_32
|
|
#define atomic_cmpset_rel_int atomic_cmpset_rel_32
|
|
#define atomic_fcmpset_int atomic_fcmpset_32
|
|
#define atomic_fcmpset_acq_int atomic_fcmpset_acq_32
|
|
#define atomic_fcmpset_rel_int atomic_fcmpset_rel_32
|
|
#define atomic_load_acq_int atomic_load_acq_32
|
|
#define atomic_store_rel_int atomic_store_rel_32
|
|
#define atomic_readandclear_int atomic_readandclear_32
|
|
#define atomic_readandset_int atomic_readandset_32
|
|
#define atomic_fetchadd_int atomic_fetchadd_32
|
|
|
|
/*
|
|
* I think the following is right, even for n32. For n32 the pointers
|
|
* are still 32-bits, so we need to operate on them as 32-bit quantities,
|
|
* even though they are sign extended in operation. For longs, there's
|
|
* no question because they are always 32-bits.
|
|
*/
|
|
#ifdef __mips_n64
|
|
/* Operations on longs. */
|
|
#define atomic_set_long atomic_set_64
|
|
#define atomic_set_acq_long atomic_set_acq_64
|
|
#define atomic_set_rel_long atomic_set_rel_64
|
|
#define atomic_clear_long atomic_clear_64
|
|
#define atomic_clear_acq_long atomic_clear_acq_64
|
|
#define atomic_clear_rel_long atomic_clear_rel_64
|
|
#define atomic_add_long atomic_add_64
|
|
#define atomic_add_acq_long atomic_add_acq_64
|
|
#define atomic_add_rel_long atomic_add_rel_64
|
|
#define atomic_subtract_long atomic_subtract_64
|
|
#define atomic_subtract_acq_long atomic_subtract_acq_64
|
|
#define atomic_subtract_rel_long atomic_subtract_rel_64
|
|
#define atomic_cmpset_long atomic_cmpset_64
|
|
#define atomic_cmpset_acq_long atomic_cmpset_acq_64
|
|
#define atomic_cmpset_rel_long atomic_cmpset_rel_64
|
|
#define atomic_fcmpset_long atomic_fcmpset_64
|
|
#define atomic_fcmpset_acq_long atomic_fcmpset_acq_64
|
|
#define atomic_fcmpset_rel_long atomic_fcmpset_rel_64
|
|
#define atomic_load_acq_long atomic_load_acq_64
|
|
#define atomic_store_rel_long atomic_store_rel_64
|
|
#define atomic_fetchadd_long atomic_fetchadd_64
|
|
#define atomic_readandclear_long atomic_readandclear_64
|
|
|
|
#else /* !__mips_n64 */
|
|
|
|
/* Operations on longs. */
|
|
#define atomic_set_long(p, v) \
|
|
atomic_set_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_set_acq_long(p, v) \
|
|
atomic_set_acq_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_set_rel_long(p, v) \
|
|
atomic_set_rel_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_clear_long(p, v) \
|
|
atomic_clear_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_clear_acq_long(p, v) \
|
|
atomic_clear_acq_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_clear_rel_long(p, v) \
|
|
atomic_clear_rel_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_add_long(p, v) \
|
|
atomic_add_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_add_acq_long(p, v) \
|
|
atomic_add_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_add_rel_long(p, v) \
|
|
atomic_add_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_subtract_long(p, v) \
|
|
atomic_subtract_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_subtract_acq_long(p, v) \
|
|
atomic_subtract_acq_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_subtract_rel_long(p, v) \
|
|
atomic_subtract_rel_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_cmpset_long(p, cmpval, newval) \
|
|
atomic_cmpset_32((volatile u_int *)(p), (u_int)(cmpval), \
|
|
(u_int)(newval))
|
|
#define atomic_cmpset_acq_long(p, cmpval, newval) \
|
|
atomic_cmpset_acq_32((volatile u_int *)(p), (u_int)(cmpval), \
|
|
(u_int)(newval))
|
|
#define atomic_cmpset_rel_long(p, cmpval, newval) \
|
|
atomic_cmpset_rel_32((volatile u_int *)(p), (u_int)(cmpval), \
|
|
(u_int)(newval))
|
|
#define atomic_fcmpset_long(p, cmpval, newval) \
|
|
atomic_fcmpset_32((volatile u_int *)(p), (u_int *)(cmpval), \
|
|
(u_int)(newval))
|
|
#define atomic_fcmpset_acq_long(p, cmpval, newval) \
|
|
atomic_fcmpset_acq_32((volatile u_int *)(p), (u_int *)(cmpval), \
|
|
(u_int)(newval))
|
|
#define atomic_fcmpset_rel_long(p, cmpval, newval) \
|
|
atomic_fcmpset_rel_32((volatile u_int *)(p), (u_int *)(cmpval), \
|
|
(u_int)(newval))
|
|
#define atomic_load_acq_long(p) \
|
|
(u_long)atomic_load_acq_32((volatile u_int *)(p))
|
|
#define atomic_store_rel_long(p, v) \
|
|
atomic_store_rel_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_fetchadd_long(p, v) \
|
|
atomic_fetchadd_32((volatile u_int *)(p), (u_int)(v))
|
|
#define atomic_readandclear_long(p) \
|
|
atomic_readandclear_32((volatile u_int *)(p))
|
|
|
|
#endif /* __mips_n64 */
|
|
|
|
/* Operations on pointers. */
|
|
#define atomic_set_ptr atomic_set_long
|
|
#define atomic_set_acq_ptr atomic_set_acq_long
|
|
#define atomic_set_rel_ptr atomic_set_rel_long
|
|
#define atomic_clear_ptr atomic_clear_long
|
|
#define atomic_clear_acq_ptr atomic_clear_acq_long
|
|
#define atomic_clear_rel_ptr atomic_clear_rel_long
|
|
#define atomic_add_ptr atomic_add_long
|
|
#define atomic_add_acq_ptr atomic_add_acq_long
|
|
#define atomic_add_rel_ptr atomic_add_rel_long
|
|
#define atomic_subtract_ptr atomic_subtract_long
|
|
#define atomic_subtract_acq_ptr atomic_subtract_acq_long
|
|
#define atomic_subtract_rel_ptr atomic_subtract_rel_long
|
|
#define atomic_cmpset_ptr atomic_cmpset_long
|
|
#define atomic_cmpset_acq_ptr atomic_cmpset_acq_long
|
|
#define atomic_cmpset_rel_ptr atomic_cmpset_rel_long
|
|
#define atomic_fcmpset_ptr atomic_fcmpset_long
|
|
#define atomic_fcmpset_acq_ptr atomic_fcmpset_acq_long
|
|
#define atomic_fcmpset_rel_ptr atomic_fcmpset_rel_long
|
|
#define atomic_load_acq_ptr atomic_load_acq_long
|
|
#define atomic_store_rel_ptr atomic_store_rel_long
|
|
#define atomic_readandclear_ptr atomic_readandclear_long
|
|
|
|
static __inline unsigned int
|
|
atomic_swap_int(volatile unsigned int *ptr, const unsigned int value)
|
|
{
|
|
unsigned int retval;
|
|
|
|
retval = *ptr;
|
|
|
|
while (!atomic_fcmpset_int(ptr, &retval, value))
|
|
;
|
|
return (retval);
|
|
}
|
|
|
|
static __inline uint32_t
|
|
atomic_swap_32(volatile uint32_t *ptr, const uint32_t value)
|
|
{
|
|
uint32_t retval;
|
|
|
|
retval = *ptr;
|
|
|
|
while (!atomic_fcmpset_32(ptr, &retval, value))
|
|
;
|
|
return (retval);
|
|
}
|
|
|
|
#if defined(__mips_n64) || defined(__mips_n32)
|
|
static __inline uint64_t
|
|
atomic_swap_64(volatile uint64_t *ptr, const uint64_t value)
|
|
{
|
|
uint64_t retval;
|
|
|
|
retval = *ptr;
|
|
|
|
while (!atomic_fcmpset_64(ptr, &retval, value))
|
|
;
|
|
return (retval);
|
|
}
|
|
#endif
|
|
|
|
#ifdef __mips_n64
|
|
static __inline unsigned long
|
|
atomic_swap_long(volatile unsigned long *ptr, const unsigned long value)
|
|
{
|
|
unsigned long retval;
|
|
|
|
retval = *ptr;
|
|
|
|
while (!atomic_fcmpset_64((volatile uint64_t *)ptr,
|
|
(uint64_t *)&retval, value))
|
|
;
|
|
return (retval);
|
|
}
|
|
#else
|
|
static __inline unsigned long
|
|
atomic_swap_long(volatile unsigned long *ptr, const unsigned long value)
|
|
{
|
|
unsigned long retval;
|
|
|
|
retval = *ptr;
|
|
|
|
while (!atomic_fcmpset_32((volatile uint32_t *)ptr,
|
|
(uint32_t *)&retval, value))
|
|
;
|
|
return (retval);
|
|
}
|
|
#endif
|
|
#define atomic_swap_ptr(ptr, value) atomic_swap_long((unsigned long *)(ptr), value)
|
|
|
|
#include <sys/_atomic_subword.h>
|
|
|
|
#endif /* ! _MACHINE_ATOMIC_H_ */
|