19d3b47b92
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
277 lines
6.5 KiB
C
277 lines
6.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD
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* $FreeBSD$
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*/
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#ifndef __NLM_MIPS_EXTNS_H__
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#define __NLM_MIPS_EXTNS_H__
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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static __inline__ int32_t nlm_swapw(int32_t *loc, int32_t val)
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{
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int32_t oldval = 0;
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__asm__ __volatile__ (
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".set push\n"
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".set noreorder\n"
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"move $9, %2\n"
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"move $8, %3\n"
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".word 0x71280014\n" /* "swapw $8, $9\n" */
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"move %1, $8\n"
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".set pop\n"
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: "+m" (*loc), "=r" (oldval)
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: "r" (loc), "r" (val)
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: "$8", "$9" );
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return oldval;
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}
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static __inline__ uint32_t nlm_swapwu(int32_t *loc, uint32_t val)
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{
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uint32_t oldval;
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__asm__ __volatile__ (
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".set push\n"
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".set noreorder\n"
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"move $9, %2\n"
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"move $8, %3\n"
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".word 0x71280015\n" /* "swapwu $8, $9\n" */
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"move %1, $8\n"
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".set pop\n"
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: "+m" (*loc), "=r" (oldval)
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: "r" (loc), "r" (val)
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: "$8", "$9" );
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return oldval;
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}
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#if (__mips == 64)
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static __inline__ uint64_t nlm_swapd(int32_t *loc, uint64_t val)
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{
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uint64_t oldval;
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__asm__ __volatile__ (
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".set push\n"
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".set noreorder\n"
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"move $9, %2\n"
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"move $8, %3\n"
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".word 0x71280014\n" /* "swapw $8, $9\n" */
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"move %1, $8\n"
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".set pop\n"
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: "+m" (*loc), "=r" (oldval)
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: "r" (loc), "r" (val)
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: "$8", "$9" );
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return oldval;
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}
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#endif
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/*
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* Atomic increment a unsigned int
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*/
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static __inline unsigned int
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nlm_ldaddwu(unsigned int value, unsigned int *addr)
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{
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__asm__ __volatile__(
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".set push\n"
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".set noreorder\n"
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"move $8, %2\n"
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"move $9, %3\n"
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".word 0x71280011\n" /* ldaddwu $8, $9 */
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"move %0, $8\n"
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".set pop\n"
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: "=&r"(value), "+m"(*addr)
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: "0"(value), "r" ((unsigned long)addr)
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: "$8", "$9");
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return (value);
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}
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/*
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* 32 bit read write for c0
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*/
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#define read_c0_register32(reg, sel) \
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({ \
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uint32_t __rv; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips32\n\t" \
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"mfc0 %0, $%1, %2\n\t" \
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".set pop\n" \
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: "=r" (__rv) : "i" (reg), "i" (sel) ); \
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__rv; \
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})
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#define write_c0_register32(reg, sel, value) \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips32\n\t" \
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"mtc0 %0, $%1, %2\n\t" \
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".set pop\n" \
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: : "r" (value), "i" (reg), "i" (sel) );
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#if defined(__mips_n64) || defined(__mips_n32)
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/*
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* On 64 bit compilation, the operations are simple
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*/
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#define read_c0_register64(reg, sel) \
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({ \
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uint64_t __rv; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips64\n\t" \
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"dmfc0 %0, $%1, %2\n\t" \
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".set pop\n" \
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: "=r" (__rv) : "i" (reg), "i" (sel) ); \
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__rv; \
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})
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#define write_c0_register64(reg, sel, value) \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips64\n\t" \
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"dmtc0 %0, $%1, %2\n\t" \
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".set pop\n" \
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: : "r" (value), "i" (reg), "i" (sel) );
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#else /* ! (defined(__mips_n64) || defined(__mips_n32)) */
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/*
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* 32 bit compilation, 64 bit values has to split
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*/
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#define read_c0_register64(reg, sel) \
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({ \
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uint32_t __high, __low; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips64\n\t" \
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"dmfc0 $8, $%2, %3\n\t" \
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"dsra32 %0, $8, 0\n\t" \
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"sll %1, $8, 0\n\t" \
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".set pop\n" \
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: "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \
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: "$8"); \
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((uint64_t)__high << 32) | __low; \
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})
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#define write_c0_register64(reg, sel, value) \
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do { \
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uint32_t __high = value >> 32; \
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uint32_t __low = value & 0xffffffff; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips64\n\t" \
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"dsll32 $8, %1, 0\n\t" \
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"dsll32 $9, %0, 0\n\t" \
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"dsrl32 $8, $8, 0\n\t" \
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"or $8, $8, $9\n\t" \
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"dmtc0 $8, $%2, %3\n\t" \
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".set pop" \
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:: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \
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:"$8", "$9"); \
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} while(0)
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#endif
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/* functions to write to and read from the extended
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* cp0 registers.
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* EIRR : Extended Interrupt Request Register
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* cp0 register 9 sel 6
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* bits 0...7 are same as cause register 8...15
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* EIMR : Extended Interrupt Mask Register
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* cp0 register 9 sel 7
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* bits 0...7 are same as status register 8...15
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*/
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static __inline uint64_t
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nlm_read_c0_eirr(void)
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{
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return (read_c0_register64(9, 6));
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}
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static __inline void
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nlm_write_c0_eirr(uint64_t val)
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{
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write_c0_register64(9, 6, val);
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}
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static __inline uint64_t
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nlm_read_c0_eimr(void)
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{
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return (read_c0_register64(9, 7));
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}
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static __inline void
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nlm_write_c0_eimr(uint64_t val)
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{
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write_c0_register64(9, 7, val);
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}
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static __inline__ uint32_t
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nlm_read_c0_ebase(void)
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{
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return (read_c0_register32(15, 1));
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}
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static __inline__ int
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nlm_nodeid(void)
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{
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return (nlm_read_c0_ebase() >> 5) & 0x3;
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}
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static __inline__ int
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nlm_cpuid(void)
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{
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return nlm_read_c0_ebase() & 0x1f;
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}
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static __inline__ int
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nlm_threadid(void)
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{
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return nlm_read_c0_ebase() & 0x3;
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}
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static __inline__ int
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nlm_coreid(void)
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{
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return (nlm_read_c0_ebase() >> 2) & 0x7;
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}
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#endif
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#define XLP_MAX_NODES 4
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#define XLP_MAX_CORES 8
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#define XLP_MAX_THREADS 4
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#endif
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