Marius Strobl 6dea80e699 - According to section 2.2.5 of the SDHCI specification version 4.20, ... SDHCI_TRNS_ACMD12 is to be set only for multiple-block read/write commands without data length information, so don't unconditionally set this bit. The result matches what e. g. Linux does. - Section 2.2.19 of the SDHCI specification version 4.20 states that SDHCI_ACMD12_ERR should be only valid if SDHCI_INT_ACMD12ERR is set and hardware may clear SDHCI_ACMD12_ERR when SDHCI_INT_ACMD12ERR is cleared (differing silicon behavior is specifically allowed, though). Thus, read SDHCI_ACMD12_ERR before clearing SDHCI_INT_ACMD12ERR. While at it, use the 16-bit accessor rather than the 32-bit one for reading the 16-bit SDHCI_ACMD12_ERR. - SDHCI_INT_TUNEERR isn't one of the ROC bits in SDHCI_INT_STATUS so clear it explicitly. - Add missing prototypes and sort them.		2018-08-23 17:50:41 +00:00
..
fsl_sdhci.c	Don't call sdhci_cleanup_slot() if sdhci_init_slot() never got called.	2018-02-17 23:39:10 +00:00
sdhci_acpi.c	The broken DDR52 support of Intel Bay Trail eMMC controllers rumored	2018-05-14 21:46:06 +00:00
sdhci_fdt_gpio.c
sdhci_fdt_gpio.h
sdhci_fdt.c	Fix build when option MMCCAM is defined.	2018-03-08 22:49:36 +00:00
sdhci_if.m
sdhci_pci.c	The broken DDR52 support of Intel Bay Trail eMMC controllers rumored	2018-05-14 21:46:06 +00:00
sdhci_xenon.c	Add support to the Marvell Xenon SDHCI controller.	2018-08-14 16:33:30 +00:00
sdhci_xenon.h	Add support to the Marvell Xenon SDHCI controller.	2018-08-14 16:33:30 +00:00
sdhci.c	- According to section 2.2.5 of the SDHCI specification version 4.20,	2018-08-23 17:50:41 +00:00
sdhci.h