96 lines
3.4 KiB
C
96 lines
3.4 KiB
C
/* $FreeBSD$ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Lennart Augustsson (lennart@augustsson.net) at
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* Carlstedt Research & Technology.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _UHCIREG_H_
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#define _UHCIREG_H_
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#define PCI_UHCI_BASE_REG 0x20
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/* PCI config registers */
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#define PCI_USBREV 0x60 /* USB protocol revision */
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#define PCI_USB_REV_MASK 0xff
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#define PCI_USB_REV_PRE_1_0 0x00
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#define PCI_USB_REV_1_0 0x10
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#define PCI_USB_REV_1_1 0x11
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#define PCI_LEGSUP 0xc0 /* Legacy Support register */
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#define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */
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#define PCI_CBIO 0x20 /* configuration base IO */
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#define PCI_INTERFACE_UHCI 0x00
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/* UHCI registers */
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#define UHCI_CMD 0x00
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#define UHCI_CMD_RS 0x0001
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#define UHCI_CMD_HCRESET 0x0002
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#define UHCI_CMD_GRESET 0x0004
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#define UHCI_CMD_EGSM 0x0008
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#define UHCI_CMD_FGR 0x0010
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#define UHCI_CMD_SWDBG 0x0020
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#define UHCI_CMD_CF 0x0040
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#define UHCI_CMD_MAXP 0x0080
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#define UHCI_STS 0x02
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#define UHCI_STS_USBINT 0x0001
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#define UHCI_STS_USBEI 0x0002
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#define UHCI_STS_RD 0x0004
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#define UHCI_STS_HSE 0x0008
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#define UHCI_STS_HCPE 0x0010
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#define UHCI_STS_HCH 0x0020
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#define UHCI_STS_ALLINTRS 0x003f
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#define UHCI_INTR 0x04
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#define UHCI_INTR_TOCRCIE 0x0001
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#define UHCI_INTR_RIE 0x0002
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#define UHCI_INTR_IOCE 0x0004
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#define UHCI_INTR_SPIE 0x0008
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#define UHCI_FRNUM 0x06
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#define UHCI_FRNUM_MASK 0x03ff
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#define UHCI_FLBASEADDR 0x08
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#define UHCI_SOF 0x0c
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#define UHCI_SOF_MASK 0x7f
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#define UHCI_PORTSC1 0x010
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#define UHCI_PORTSC2 0x012
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#define UHCI_PORTSC_CCS 0x0001
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#define UHCI_PORTSC_CSC 0x0002
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#define UHCI_PORTSC_PE 0x0004
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#define UHCI_PORTSC_POEDC 0x0008
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#define UHCI_PORTSC_LS 0x0030
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#define UHCI_PORTSC_LS_SHIFT 4
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#define UHCI_PORTSC_RD 0x0040
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#define UHCI_PORTSC_LSDA 0x0100
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#define UHCI_PORTSC_PR 0x0200
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#define UHCI_PORTSC_OCI 0x0400
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#define UHCI_PORTSC_OCIC 0x0800
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#define UHCI_PORTSC_SUSP 0x1000
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#define URWMASK(x) ((x) & (UHCI_PORTSC_SUSP | \
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UHCI_PORTSC_PR | UHCI_PORTSC_RD | \
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UHCI_PORTSC_PE))
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#endif /* _UHCIREG_H_ */
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