ddfc9c4c59
Now that the upper layers all go through a layer to tie into these
information functions that translates an sbuf into char * and len. The
current interface suffers issues of what to do in cases of truncation,
etc. Instead, migrate all these functions to using struct sbuf and these
issues go away. The caller is also in charge of any memory allocation
and/or expansion that's needed during this process.
Create a bus_generic_child_{pnpinfo,location} and make it default. It
just returns success. This is for those busses that have no information
for these items. Migrate the now-empty routines to using this as
appropriate.
Document these new interfaces with man pages, and oversight from before.
Reviewed by: jhb, bcr
Sponsored by: Netflix
Differential Revision: https://reviews.freebsd.org/D29937
425 lines
12 KiB
C
425 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2020 Alstom Group
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* Copyright (c) 2020 Semihalf
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* AHCI controller driver for NXP QorIQ Layerscape SoCs. */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/stdint.h>
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#include <sys/stddef.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/module.h>
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#include <sys/sysctl.h>
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#include <sys/rman.h>
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#include <sys/unistd.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ahci/ahci.h>
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#include <dev/extres/clk/clk.h>
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#define AHCI_FSL_REG_PHY1 0xa8
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#define AHCI_FSL_REG_PHY2 0xac
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#define AHCI_FSL_REG_PHY3 0xb0
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#define AHCI_FSL_REG_PHY4 0xb4
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#define AHCI_FSL_REG_PHY5 0xb8
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#define AHCI_FSL_REG_AXICC 0xbc
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#define AHCI_FSL_REG_PTC 0xc8
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#define AHCI_FSL_LS1021A_AXICC 0xc0
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#define AHCI_FSL_REG_PHY1_TTA_MASK 0x0001ffff
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#define AHCI_FSL_REG_PHY1_SNM (1 << 17)
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#define AHCI_FSL_REG_PHY1_SNR (1 << 18)
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#define AHCI_FSL_REG_PHY1_FPR (1 << 20)
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#define AHCI_FSL_REG_PHY1_PBPS_LBP 0
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#define AHCI_FSL_REG_PHY1_PBPS_LFTP (0x01 << 21)
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#define AHCI_FSL_REG_PHY1_PBPS_MFTP (0x02 << 21)
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#define AHCI_FSL_REG_PHY1_PBPS_HFTP (0x03 << 21)
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#define AHCI_FSL_REG_PHY1_PBPS_PRBS (0x04 << 21)
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#define AHCI_FSL_REG_PHY1_PBPS_BIST (0x05 << 21)
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#define AHCI_FSL_REG_PHY1_PBPE (1 << 24)
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#define AHCI_FSL_REG_PHY1_PBCE (1 << 25)
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#define AHCI_FSL_REG_PHY1_PBPNA (1 << 26)
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#define AHCI_FSL_REG_PHY1_STB (1 << 27)
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#define AHCI_FSL_REG_PHY1_PSSO (1 << 28)
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#define AHCI_FSL_REG_PHY1_PSS (1 << 29)
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#define AHCI_FSL_REG_PHY1_ERSN (1 << 30)
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#define AHCI_FSL_REG_PHY1_ESDF (1 << 31)
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#define AHCI_FSL_REG_PHY_MASK 0xff
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#define AHCI_FSL_PHY2_CIBGMN_SHIFT 0
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#define AHCI_FSL_PHY2_CIBGMX_SHIFT 8
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#define AHCI_FSL_PHY2_CIBGN_SHIFT 16
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#define AHCI_FSL_PHY2_CINMP_SHIFT 24
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#define AHCI_FSL_PHY3_CWBGMN_SHIFT 0
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#define AHCI_FSL_PHY3_CWBGMX_SHIFT 8
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#define AHCI_FSL_PHY3_CWBGN_SHIFT 16
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#define AHCI_FSL_PHY3_CWNMP_SHIFT 24
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/* Only in LS1021A */
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#define AHCI_FSL_PHY4_BMX_SHIFT 0
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#define AHCI_FSL_PHY4_BNM_SHIFT 8
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#define AHCI_FSL_PHY4_SFD_SHIFT 16
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#define AHCI_FSL_PHY4_PTST_SHIFT 24
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/* Only in LS1021A */
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#define AHCI_FSL_PHY5_RIT_SHIFT 0
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#define AHCI_FSL_PHY5_RCT_SHIFT 20
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#define AHCI_FSL_REG_PTC_RXWM_MASK 0x0000007f
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#define AHCI_FSL_REG_PTC_ENBD (1 << 8)
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#define AHCI_FSL_REG_PTC_ITM (1 << 9)
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#define AHCI_FSL_REG_PHY1_CFG \
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((0x1fffe & AHCI_FSL_REG_PHY1_TTA_MASK) | \
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AHCI_FSL_REG_PHY1_SNM | AHCI_FSL_REG_PHY1_PSS | AHCI_FSL_REG_PHY1_ESDF)
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#define AHCI_FSL_REG_PHY2_CFG \
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((0x1f << AHCI_FSL_PHY2_CIBGMN_SHIFT) | \
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(0x4d << AHCI_FSL_PHY2_CIBGMX_SHIFT) | \
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(0x18 << AHCI_FSL_PHY2_CIBGN_SHIFT) | \
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(0x28 << AHCI_FSL_PHY2_CINMP_SHIFT))
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#define AHCI_FSL_REG_PHY2_CFG_LS1021A \
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((0x14 << AHCI_FSL_PHY2_CIBGMN_SHIFT) | \
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(0x34 << AHCI_FSL_PHY2_CIBGMX_SHIFT) | \
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(0x18 << AHCI_FSL_PHY2_CIBGN_SHIFT) | \
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(0x28 << AHCI_FSL_PHY2_CINMP_SHIFT))
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#define AHCI_FSL_REG_PHY3_CFG \
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((0x09 << AHCI_FSL_PHY3_CWBGMN_SHIFT) | \
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(0x15 << AHCI_FSL_PHY3_CWBGMX_SHIFT) | \
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(0x08 << AHCI_FSL_PHY3_CWBGN_SHIFT) | \
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(0x0e << AHCI_FSL_PHY3_CWNMP_SHIFT))
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#define AHCI_FSL_REG_PHY3_CFG_LS1021A \
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((0x06 << AHCI_FSL_PHY3_CWBGMN_SHIFT) | \
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(0x0e << AHCI_FSL_PHY3_CWBGMX_SHIFT) | \
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(0x08 << AHCI_FSL_PHY3_CWBGN_SHIFT) | \
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(0x0e << AHCI_FSL_PHY3_CWNMP_SHIFT))
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#define AHCI_FSL_REG_PHY4_CFG_LS1021A \
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((0x0b << AHCI_FSL_PHY4_BMX_SHIFT) | \
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(0x08 << AHCI_FSL_PHY4_BNM_SHIFT) | \
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(0x4a << AHCI_FSL_PHY4_SFD_SHIFT) | \
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(0x06 << AHCI_FSL_PHY4_PTST_SHIFT))
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#define AHCI_FSL_REG_PHY5_CFG_LS1021A \
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((0x86470 << AHCI_FSL_PHY5_RIT_SHIFT) | \
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(0x2aa << AHCI_FSL_PHY5_RCT_SHIFT))
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/* Bit 27 enabled so value of reserved bits remains as in documentation. */
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#define AHCI_FSL_REG_PTC_CFG \
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((0x29 & AHCI_FSL_REG_PTC_RXWM_MASK) | (1 << 27))
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#define AHCI_FSL_REG_AXICC_CFG 0x3fffffff
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#define AHCI_FSL_REG_ECC 0x0
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#define AHCI_FSL_REG_ECC_LS1021A 0x00020000
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#define AHCI_FSL_REG_ECC_LS1043A 0x80000000
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#define AHCI_FSL_REG_ECC_LS1028A 0x40000000
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#define QORIQ_AHCI_LS1021A 1
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#define QORIQ_AHCI_LS1028A 2
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#define QORIQ_AHCI_LS1043A 3
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#define QORIQ_AHCI_LS2080A 4
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#define QORIQ_AHCI_LS1046A 5
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#define QORIQ_AHCI_LS1088A 6
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#define QORIQ_AHCI_LS2088A 7
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#define QORIQ_AHCI_LX2160A 8
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struct ahci_fsl_fdt_controller {
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struct ahci_controller ctlr; /* Must be the first field. */
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int soc_type;
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struct resource *r_ecc;
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int r_ecc_rid;
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};
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static const struct ofw_compat_data ahci_fsl_fdt_compat_data[] = {
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{"fsl,ls1021a-ahci", QORIQ_AHCI_LS1021A},
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{"fsl,ls1028a-ahci", QORIQ_AHCI_LS1028A},
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{"fsl,ls1043a-ahci", QORIQ_AHCI_LS1043A},
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{"fsl,ls2080a-ahci", QORIQ_AHCI_LS2080A},
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{"fsl,ls1046a-ahci", QORIQ_AHCI_LS1046A},
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{"fsl,ls1088a-ahci", QORIQ_AHCI_LS1088A},
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{"fsl,ls2088a-ahci", QORIQ_AHCI_LS2088A},
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{"fsl,lx2160a-ahci", QORIQ_AHCI_LX2160A},
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{NULL, 0}
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};
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static bool ecc_inited;
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static int
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ahci_fsl_fdt_ecc_init(struct ahci_fsl_fdt_controller *ctrl)
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{
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uint32_t val;
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switch (ctrl->soc_type) {
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case QORIQ_AHCI_LS2080A:
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case QORIQ_AHCI_LS2088A:
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return (0);
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case QORIQ_AHCI_LS1021A:
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if (!ecc_inited && ctrl->r_ecc == NULL)
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return (ENXIO);
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if (!ecc_inited)
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ATA_OUTL(ctrl->r_ecc, AHCI_FSL_REG_ECC,
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AHCI_FSL_REG_ECC_LS1021A);
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break;
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case QORIQ_AHCI_LS1043A:
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case QORIQ_AHCI_LS1046A:
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if (!ecc_inited && ctrl->r_ecc == NULL)
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return (ENXIO);
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if (!ecc_inited) {
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val = ATA_INL(ctrl->r_ecc, AHCI_FSL_REG_ECC);
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val = AHCI_FSL_REG_ECC_LS1043A;
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ATA_OUTL(ctrl->r_ecc, AHCI_FSL_REG_ECC, val);
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}
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break;
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case QORIQ_AHCI_LS1028A:
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case QORIQ_AHCI_LS1088A:
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case QORIQ_AHCI_LX2160A:
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if (!ecc_inited && ctrl->r_ecc == NULL)
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return (ENXIO);
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if (!ecc_inited) {
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val = ATA_INL(ctrl->r_ecc, AHCI_FSL_REG_ECC);
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val |= AHCI_FSL_REG_ECC_LS1028A;
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ATA_OUTL(ctrl->r_ecc, AHCI_FSL_REG_ECC, val);
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}
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break;
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default:
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panic("Unimplemented SOC type: %d", ctrl->soc_type);
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}
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ecc_inited = true;
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return (0);
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}
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static void
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ahci_fsl_fdt_phy_init(struct ahci_fsl_fdt_controller *ctrl)
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{
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struct ahci_controller *ahci;
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ahci = &ctrl->ctlr;
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if (ctrl->soc_type == QORIQ_AHCI_LS1021A) {
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ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PHY1,
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AHCI_FSL_REG_PHY1_CFG);
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ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PHY2,
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AHCI_FSL_REG_PHY2_CFG_LS1021A);
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ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PHY3,
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AHCI_FSL_REG_PHY3_CFG_LS1021A);
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ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PHY4,
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AHCI_FSL_REG_PHY4_CFG_LS1021A);
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ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PHY5,
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AHCI_FSL_REG_PHY5_CFG_LS1021A);
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ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PTC,
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AHCI_FSL_REG_PTC_CFG);
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if (ctrl->ctlr.dma_coherent)
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ATA_OUTL(ahci->r_mem, AHCI_FSL_LS1021A_AXICC,
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AHCI_FSL_REG_AXICC_CFG);
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} else {
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ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PHY1,
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AHCI_FSL_REG_PHY1_CFG);
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ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PHY2,
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AHCI_FSL_REG_PHY2_CFG);
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ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PHY3,
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AHCI_FSL_REG_PHY3_CFG);
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ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PTC,
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AHCI_FSL_REG_PTC_CFG);
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if (ctrl->ctlr.dma_coherent)
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ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_AXICC,
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AHCI_FSL_REG_AXICC_CFG);
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}
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}
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static int
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ahci_fsl_fdt_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, ahci_fsl_fdt_compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "NXP QorIQ Layerscape AHCI controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ahci_fsl_fdt_attach(device_t dev)
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{
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struct ahci_fsl_fdt_controller *ctlr;
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struct ahci_controller *ahci;
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phandle_t node;
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clk_t clock;
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int ret;
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node = ofw_bus_get_node(dev);
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ctlr = device_get_softc(dev);
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ctlr->soc_type =
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ofw_bus_search_compatible(dev, ahci_fsl_fdt_compat_data)->ocd_data;
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ahci = &ctlr->ctlr;
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ahci->dev = dev;
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ahci->r_rid = 0;
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ahci->quirks = AHCI_Q_NOPMP;
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ahci->dma_coherent = OF_hasprop(node, "dma-coherent");
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ret = clk_get_by_ofw_index(dev, node, 0, &clock);
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if (ret != 0) {
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device_printf(dev, "No clock found.\n");
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return (ENXIO);
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}
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ret = clk_enable(clock);
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if (ret !=0) {
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device_printf(dev, "Could not enable clock.\n");
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return (ENXIO);
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}
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if (OF_hasprop(node, "reg-names") && ofw_bus_find_string_index(node,
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"reg-names", "ahci", &ahci->r_rid)) {
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device_printf(dev, "Could not locate 'ahci' string in the "
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"'reg-names' property");
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return (ENOENT);
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}
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ahci->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&ahci->r_rid, RF_ACTIVE);
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if (!ahci->r_mem) {
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device_printf(dev,
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"Could not allocate resources for controller\n");
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return (ENOMEM);
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}
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ret = ofw_bus_find_string_index(node, "reg-names", "sata-ecc",
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&ctlr->r_ecc_rid);
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if (ret == 0) {
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ctlr->r_ecc = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&ctlr->r_ecc_rid, RF_ACTIVE| RF_SHAREABLE);
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if (!ctlr->r_ecc) {
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device_printf(dev,
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"Could not allocate resources for controller\n");
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ret = ENOMEM;
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goto err_free_mem;
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}
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} else if (ret != ENOENT) {
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device_printf(dev, "Could not locate 'sata-ecc' string in "
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"the 'reg-names' property");
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goto err_free_mem;
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}
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ret = ahci_fsl_fdt_ecc_init(ctlr);
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if (ret != 0) {
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device_printf(dev, "Could not initialize 'ecc' registers");
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goto err_free_mem;
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}
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/* Setup controller defaults. */
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ahci->numirqs = 1;
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ahci_fsl_fdt_phy_init(ctlr);
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/* Reset controller. */
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ret = ahci_ctlr_reset(dev);
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if (ret)
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goto err_free_mem;
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ret = ahci_attach(dev);
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if (ret) {
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device_printf(dev,
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"Could not initialize AHCI, with error: %d\n", ret);
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goto err_free_ecc;
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}
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return (0);
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err_free_mem:
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bus_free_resource(dev, SYS_RES_MEMORY, ahci->r_mem);
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err_free_ecc:
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if (ctlr->r_ecc)
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bus_free_resource(dev, SYS_RES_MEMORY, ctlr->r_ecc);
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return (ret);
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}
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static int
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ahci_fsl_fdt_detach(device_t dev)
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{
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struct ahci_fsl_fdt_controller *ctlr;
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ctlr = device_get_softc(dev);
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if (ctlr->r_ecc)
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bus_free_resource(dev, SYS_RES_MEMORY, ctlr->r_ecc);
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return ahci_detach(dev);
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}
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static const device_method_t ahci_fsl_fdt_methods[] = {
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DEVMETHOD(device_probe, ahci_fsl_fdt_probe),
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DEVMETHOD(device_attach, ahci_fsl_fdt_attach),
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DEVMETHOD(device_detach, ahci_fsl_fdt_detach),
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DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
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DEVMETHOD(bus_release_resource, ahci_release_resource),
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DEVMETHOD(bus_setup_intr, ahci_setup_intr),
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DEVMETHOD(bus_teardown_intr, ahci_teardown_intr),
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DEVMETHOD(bus_print_child, ahci_print_child),
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DEVMETHOD(bus_child_location, ahci_child_location),
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DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag),
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t ahci_fsl_fdt_driver = {
|
|
"ahci",
|
|
ahci_fsl_fdt_methods,
|
|
sizeof(struct ahci_fsl_fdt_controller),
|
|
};
|
|
|
|
static devclass_t ahci_fsl_fdt_devclass;
|
|
DRIVER_MODULE(ahci_fsl, simplebus, ahci_fsl_fdt_driver, ahci_fsl_fdt_devclass,
|
|
NULL, NULL);
|
|
DRIVER_MODULE(ahci_fsl, ofwbus, ahci_fsl_fdt_driver, ahci_fsl_fdt_devclass,
|
|
NULL, NULL);
|