733b92779e
- Device configuration via plain text config file. Also able to operate
when not attached to the chip as the master driver.
- Generic "work request" queue that serves as the base for both ctrl and
ofld tx queues.
- Generic interrupt handler routine that can process any event on any
kind of ingress queue (via a dispatch table).
- A couple of new driver ioctls. cxgbetool can now install a firmware
to the card ("loadfw" command) and can read the card's memory
("memdump" and "tcb" commands).
- Lots of assorted information within dev.t4nex.X.misc.* This is
primarily for debugging and won't show up in sysctl -a.
- Code to manage the L2 tables on the chip.
- Updates to cxgbe(4) man page to go with the tunables that have changed.
- Updates to the shared code in common/
- Updates to the driver-firmware interface (now at fw 1.4.16.0)
MFC after: 1 month
264 lines
8.2 KiB
C
264 lines
8.2 KiB
C
/*-
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* Copyright (c) 2011 Chelsio Communications, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __T4_HW_H
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#define __T4_HW_H
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#include "osdep.h"
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enum {
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NCHAN = 4, /* # of HW channels */
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MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
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EEPROMSIZE = 17408, /* Serial EEPROM physical size */
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EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
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EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
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RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
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TCB_SIZE = 128, /* TCB size */
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NMTUS = 16, /* size of MTU table */
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NCCTRL_WIN = 32, /* # of congestion control windows */
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NTX_SCHED = 8, /* # of HW Tx scheduling queues */
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PM_NSTATS = 5, /* # of PM stats */
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MBOX_LEN = 64, /* mailbox size in bytes */
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TRACE_LEN = 112, /* length of trace data and mask */
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FILTER_OPT_LEN = 36, /* filter tuple width for optional components */
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NWOL_PAT = 8, /* # of WoL patterns */
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WOL_PAT_LEN = 128, /* length of WoL patterns */
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};
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enum {
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CIM_NUM_IBQ = 6, /* # of CIM IBQs */
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CIM_NUM_OBQ = 6, /* # of CIM OBQs */
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CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
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CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
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CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
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CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
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TPLA_SIZE = 128, /* # of 64-bit words in TP LA */
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ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */
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};
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enum {
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SF_PAGE_SIZE = 256, /* serial flash page size */
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SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
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};
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/* SGE context types */
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enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM };
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enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
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enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
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enum {
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SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
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SGE_CTXT_SIZE = 24, /* size of SGE context */
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SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
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SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
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};
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struct sge_qstat { /* data written to SGE queue status entries */
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volatile __be32 qid;
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volatile __be16 cidx;
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volatile __be16 pidx;
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};
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#define S_QSTAT_PIDX 0
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#define M_QSTAT_PIDX 0xffff
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#define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
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#define S_QSTAT_CIDX 16
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#define M_QSTAT_CIDX 0xffff
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#define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
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/*
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* Structure for last 128 bits of response descriptors
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*/
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struct rsp_ctrl {
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__be32 hdrbuflen_pidx;
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__be32 pldbuflen_qid;
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union {
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u8 type_gen;
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__be64 last_flit;
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} u;
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};
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#define S_RSPD_NEWBUF 31
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#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
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#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)
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#define S_RSPD_LEN 0
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#define M_RSPD_LEN 0x7fffffff
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#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
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#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
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#define S_RSPD_QID S_RSPD_LEN
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#define M_RSPD_QID M_RSPD_LEN
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#define V_RSPD_QID(x) V_RSPD_LEN(x)
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#define G_RSPD_QID(x) G_RSPD_LEN(x)
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#define S_RSPD_GEN 7
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#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
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#define F_RSPD_GEN V_RSPD_GEN(1U)
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#define S_RSPD_QOVFL 6
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#define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
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#define F_RSPD_QOVFL V_RSPD_QOVFL(1U)
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#define S_RSPD_TYPE 4
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#define M_RSPD_TYPE 0x3
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#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
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#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
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/* Rx queue interrupt deferral fields: counter enable and timer index */
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#define S_QINTR_CNT_EN 0
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#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
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#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)
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#define S_QINTR_TIMER_IDX 1
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#define M_QINTR_TIMER_IDX 0x7
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#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
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#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
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/* # of pages a pagepod can hold without needing another pagepod */
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#define PPOD_PAGES 4U
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struct pagepod {
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__be64 vld_tid_pgsz_tag_color;
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__be64 len_offset;
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__be64 rsvd;
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__be64 addr[PPOD_PAGES + 1];
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};
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#define S_PPOD_COLOR 0
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#define M_PPOD_COLOR 0x3F
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#define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
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#define S_PPOD_TAG 6
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#define M_PPOD_TAG 0xFFFFFF
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#define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
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#define S_PPOD_PGSZ 30
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#define M_PPOD_PGSZ 0x3
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#define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
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#define S_PPOD_TID 32
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#define M_PPOD_TID 0xFFFFFF
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#define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
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#define S_PPOD_VALID 56
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#define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
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#define F_PPOD_VALID V_PPOD_VALID(1ULL)
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#define S_PPOD_LEN 32
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#define M_PPOD_LEN 0xFFFFFFFF
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#define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
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#define S_PPOD_OFST 0
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#define M_PPOD_OFST 0xFFFFFFFF
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#define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
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/*
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* Flash layout.
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*/
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#define FLASH_START(start) ((start) * SF_SEC_SIZE)
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#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
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enum {
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/*
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* Various Expansion-ROM boot images, etc.
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*/
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FLASH_EXP_ROM_START_SEC = 0,
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FLASH_EXP_ROM_NSECS = 6,
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FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
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FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
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/*
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* iSCSI Boot Firmware Table (iBFT) and other driver-related
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* parameters ...
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*/
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FLASH_IBFT_START_SEC = 6,
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FLASH_IBFT_NSECS = 1,
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FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
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FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
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/*
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* Boot configuration data.
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*/
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FLASH_BOOTCFG_START_SEC = 7,
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FLASH_BOOTCFG_NSECS = 1,
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FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
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FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
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/*
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* Location of firmware image in FLASH.
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*/
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FLASH_FW_START_SEC = 8,
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FLASH_FW_NSECS = 8,
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FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
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FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
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/*
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* iSCSI persistent/crash information.
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*/
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FLASH_ISCSI_CRASH_START_SEC = 29,
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FLASH_ISCSI_CRASH_NSECS = 1,
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FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
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FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
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/*
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* FCoE persistent/crash information.
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*/
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FLASH_FCOE_CRASH_START_SEC = 30,
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FLASH_FCOE_CRASH_NSECS = 1,
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FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
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FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
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/*
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* Location of Firmware Configuration File in FLASH. Since the FPGA
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* "FLASH" is smaller we need to store the Configuration File in a
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* different location -- which will overlap the end of the firmware
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* image if firmware ever gets that large ...
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*/
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FLASH_CFG_START_SEC = 31,
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FLASH_CFG_NSECS = 1,
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FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
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FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
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FLASH_FPGA_CFG_START_SEC = 15,
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FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
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/*
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* Sectors 32-63 are reserved for FLASH failover.
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*/
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};
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#undef FLASH_START
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#undef FLASH_MAX_SIZE
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#endif /* __T4_HW_H */
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