f11c7f6305
The isci driver is for the integrated SAS controller in the Intel C600 (Patsburg) chipset. Source files in sys/dev/isci directory are FreeBSD-specific, and sys/dev/isci/scil subdirectory contains an OS-agnostic library (SCIL) published by Intel to control the SAS controller. This library is used primarily as-is in this driver, with some post-processing to better integrate into the kernel build environment. isci.4 and a README in the sys/dev/isci directory contain a few additional details. This driver is only built for amd64 and i386 targets. Sponsored by: Intel Reviewed by: scottl Approved by: scottl
299 lines
8.4 KiB
C
299 lines
8.4 KiB
C
/*-
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/**
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* @file
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*
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* @brief This file contains the implementation of the SGPIO register inteface
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* methods.
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*/
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#include <dev/isci/scil/scic_sgpio.h>
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#include <dev/isci/scil/scic_sds_controller_registers.h>
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#include <dev/isci/scil/scic_user_callback.h>
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/**
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* @brief Function writes Value to the
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* SGPIO Output Data Select Register (SGODSR) for phys specified by
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* phy_mask paremeter
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*
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* @param[in] SCIC_SDS_CONTROLLER_T controller
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* @param[in] phy_mask - This field is a bit mask that specifies the phys
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* to be updated.
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* @param[in] value - Value for write
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*
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* @return none
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*/
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static
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void scic_sgpio_write_SGODSR_register(
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SCIC_SDS_CONTROLLER_T *controller,
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U32 phy_mask,
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U32 value
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)
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{
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U8 phy_index;
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for (phy_index = 0; phy_index < SCI_MAX_PHYS; phy_index++)
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{
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if (phy_mask >> phy_index & 1)
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{
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scu_sgpio_peg0_register_write(
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controller, output_data_select[phy_index], value
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);
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}
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}
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}
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void scic_sgpio_set_vendor_code(
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SCI_CONTROLLER_HANDLE_T controller,
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U8 vendor_specific_sequence
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)
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{
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SCIC_SDS_CONTROLLER_T * core_controller = (SCIC_SDS_CONTROLLER_T *) controller;
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scu_sgpio_peg0_register_write(
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core_controller, vendor_specific_code, vendor_specific_sequence);
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}
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void scic_sgpio_set_blink_patterns(
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SCI_CONTROLLER_HANDLE_T controller,
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U8 pattern_a_low,
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U8 pattern_a_high,
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U8 pattern_b_low,
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U8 pattern_b_high
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)
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{
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U32 value;
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SCIC_SDS_CONTROLLER_T * core_controller = (SCIC_SDS_CONTROLLER_T *) controller;
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value = (pattern_b_high << 12) + (pattern_b_low << 8) + (pattern_a_high << 4) + pattern_a_low;
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scu_sgpio_peg0_register_write(
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core_controller, blink_rate, value);
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}
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void scic_sgpio_set_functionality(
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SCI_CONTROLLER_HANDLE_T controller,
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BOOL sgpio_mode
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)
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{
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U32 value = DISABLE_SGPIO_FUNCTIONALITY;
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SCIC_SDS_CONTROLLER_T * core_controller = (SCIC_SDS_CONTROLLER_T *) controller;
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if(sgpio_mode)
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{
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value = ENABLE_SGPIO_FUNCTIONALITY;
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}
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scu_sgpio_peg0_register_write(
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core_controller, interface_control, value);
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}
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void scic_sgpio_apply_led_blink_pattern(
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SCI_CONTROLLER_HANDLE_T controller,
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U32 phy_mask,
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BOOL error,
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BOOL locate,
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BOOL activity,
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U8 pattern_selection
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)
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{
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U32 output_value = 0;
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SCIC_SDS_CONTROLLER_T * core_controller = (SCIC_SDS_CONTROLLER_T *) controller;
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// Start with all LEDs turned off
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output_value = (SGODSR_INVERT_BIT << SGODSR_ERROR_LED_SHIFT)
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| (SGODSR_INVERT_BIT << SGODSR_LOCATE_LED_SHIFT)
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| (SGODSR_INVERT_BIT << SGODSR_ACTIVITY_LED_SHIFT);
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if(error)
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{ //apply pattern to error LED
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output_value |= pattern_selection << SGODSR_ERROR_LED_SHIFT;
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output_value &= ~(SGODSR_INVERT_BIT << SGODSR_ERROR_LED_SHIFT);
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}
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if(locate)
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{ //apply pattern to locate LED
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output_value |= pattern_selection << SGODSR_LOCATE_LED_SHIFT;
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output_value &= ~(SGODSR_INVERT_BIT << SGODSR_LOCATE_LED_SHIFT);
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}
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if(activity)
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{ //apply pattern to activity LED
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output_value |= pattern_selection << SGODSR_ACTIVITY_LED_SHIFT;
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output_value &= ~(SGODSR_INVERT_BIT << SGODSR_ACTIVITY_LED_SHIFT);
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}
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scic_sgpio_write_SGODSR_register(core_controller, phy_mask, output_value);
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}
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void scic_sgpio_set_led_blink_pattern(
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SCI_CONTROLLER_HANDLE_T controller,
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SCI_PORT_HANDLE_T port_handle,
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BOOL error,
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BOOL locate,
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BOOL activity,
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U8 pattern_selection
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)
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{
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U32 phy_mask;
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SCIC_SDS_PORT_T * port = (SCIC_SDS_PORT_T *) port_handle;
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phy_mask = scic_sds_port_get_phys(port);
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scic_sgpio_apply_led_blink_pattern(
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controller, phy_mask, error, locate, activity, pattern_selection);
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}
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void scic_sgpio_update_led_state(
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SCI_CONTROLLER_HANDLE_T controller,
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U32 phy_mask,
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BOOL error,
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BOOL locate,
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BOOL activity
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)
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{
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U32 output_value;
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SCIC_SDS_CONTROLLER_T * core_controller = (SCIC_SDS_CONTROLLER_T *) controller;
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// Start with all LEDs turned on
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output_value = 0x00000000;
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if(!error)
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{ //turn off error LED
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output_value |= SGODSR_INVERT_BIT << SGODSR_ERROR_LED_SHIFT;
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}
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if(!locate)
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{ //turn off locate LED
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output_value |= SGODSR_INVERT_BIT << SGODSR_LOCATE_LED_SHIFT;
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}
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if(!activity)
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{ //turn off activity LED
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output_value |= SGODSR_INVERT_BIT << SGODSR_ACTIVITY_LED_SHIFT;
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}
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scic_sgpio_write_SGODSR_register(core_controller, phy_mask, output_value);
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}
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void scic_sgpio_set_led_state(
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SCI_CONTROLLER_HANDLE_T controller,
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SCI_PORT_HANDLE_T port_handle,
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BOOL error,
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BOOL locate,
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BOOL activity
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)
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{
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U32 phy_mask;
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SCIC_SDS_PORT_T * port = (SCIC_SDS_PORT_T *) port_handle;
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phy_mask = scic_sds_port_get_phys(port);
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scic_sgpio_update_led_state(controller, phy_mask, error, locate, activity);
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}
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void scic_sgpio_set_to_hardware_control(
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SCI_CONTROLLER_HANDLE_T controller,
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BOOL is_hardware_controlled
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)
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{
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SCIC_SDS_CONTROLLER_T * core_controller = (SCIC_SDS_CONTROLLER_T *) controller;
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U8 i;
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U32 output_value;
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//turn on hardware control for LED's
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if(is_hardware_controlled)
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{
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output_value = SGPIO_HARDWARE_CONTROL;
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}
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else //turn off hardware control
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{
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output_value = SGPIO_SOFTWARE_CONTROL;
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}
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for(i = 0; i < SCI_MAX_PHYS; i++)
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{
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scu_sgpio_peg0_register_write(
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core_controller, output_data_select[i], output_value);
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}
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}
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U32 scic_sgpio_read(
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SCI_CONTROLLER_HANDLE_T controller
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)
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{
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//Not supported in the SCU hardware returning 0xFFFFFFFF
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return 0xffffffff;
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}
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void scic_sgpio_hardware_initialize(
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SCI_CONTROLLER_HANDLE_T controller
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)
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{
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scic_sgpio_set_functionality(controller, TRUE);
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scic_sgpio_set_to_hardware_control(controller, TRUE);
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scic_sgpio_set_vendor_code(controller, 0x00);
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}
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void scic_sgpio_initialize(
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SCI_CONTROLLER_HANDLE_T controller
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)
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{
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scic_sgpio_set_functionality(controller, TRUE);
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scic_sgpio_set_to_hardware_control(controller, FALSE);
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scic_sgpio_set_vendor_code(controller, 0x00);
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}
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