134 lines
3.9 KiB
Plaintext
134 lines
3.9 KiB
Plaintext
/*
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* BSD LICENSE
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*
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* Copyright(c) 2014 Broadcom Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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/* Cygnus ARM PLL */
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armpll: armpll@19000000 {
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#clock-cells = <0>;
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compatible = "brcm,cygnus-armpll";
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clocks = <&osc>;
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reg = <0x19000000 0x1000>;
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};
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/* peripheral clock for system timer */
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periph_clk: arm_periph_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&armpll>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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/* APB bus clock */
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apb_clk: apb_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&armpll>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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genpll: genpll@301d000 {
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#clock-cells = <1>;
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compatible = "brcm,cygnus-genpll";
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reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
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clocks = <&osc>;
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clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
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"enet_sw", "audio_125", "can";
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};
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/* always 1/2 of the axi21 clock */
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axi41_clk: axi41_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&genpll 1>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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/* always 1/4 of the axi21 clock */
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axi81_clk: axi81_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&genpll 1>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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lcpll0: lcpll0@301d02c {
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#clock-cells = <1>;
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compatible = "brcm,cygnus-lcpll0";
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reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
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clocks = <&osc>;
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clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio",
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"usb_phy", "smart_card", "ch5";
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};
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mipipll: mipipll@180a9800 {
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#clock-cells = <1>;
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compatible = "brcm,cygnus-mipipll";
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reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
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clocks = <&osc>;
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clock-output-names = "mipipll", "ch0_unused", "ch1_lcd",
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"ch2_v3d", "ch3_unused", "ch4_unused",
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"ch5_unused";
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};
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asiu_clks: asiu_clks@301d048 {
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#clock-cells = <1>;
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compatible = "brcm,cygnus-asiu-clk";
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reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
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clocks = <&osc>;
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clock-output-names = "keypad", "adc/touch", "pwm";
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};
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audiopll: audiopll@180aeb00 {
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#clock-cells = <1>;
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compatible = "brcm,cygnus-audiopll";
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reg = <0x180aeb00 0x68>;
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clocks = <&osc>;
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clock-output-names = "audiopll", "ch0_audio",
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"ch1_audio", "ch2_audio";
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};
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};
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