147 lines
3.1 KiB
Plaintext
147 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
|
|
/*
|
|
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
|
|
*
|
|
* Based on "omap4.dtsi"
|
|
*/
|
|
|
|
#include "dra7.dtsi"
|
|
|
|
/ {
|
|
compatible = "ti,dra742", "ti,dra74", "ti,dra7";
|
|
|
|
cpus {
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <1>;
|
|
operating-points-v2 = <&cpu0_opp_table>;
|
|
|
|
clocks = <&dpll_mpu_ck>;
|
|
clock-names = "cpu";
|
|
|
|
clock-latency = <300000>; /* From omap-cpufreq driver */
|
|
|
|
/* cooling options */
|
|
#cooling-cells = <2>; /* min followed by max */
|
|
|
|
vbb-supply = <&abb_mpu>;
|
|
};
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a15-pmu";
|
|
interrupt-parent = <&wakeupgen>;
|
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
ocp {
|
|
dsp2_system: dsp_system@41500000 {
|
|
compatible = "syscon";
|
|
reg = <0x41500000 0x100>;
|
|
};
|
|
|
|
omap_dwc3_4: omap_dwc3_4@48940000 {
|
|
compatible = "ti,dwc3";
|
|
ti,hwmods = "usb_otg_ss4";
|
|
reg = <0x48940000 0x10000>;
|
|
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
utmi-mode = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
usb4: usb@48950000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x48950000 0x17000>;
|
|
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "peripheral",
|
|
"host",
|
|
"otg";
|
|
maximum-speed = "high-speed";
|
|
dr_mode = "otg";
|
|
};
|
|
};
|
|
|
|
mmu0_dsp2: mmu@41501000 {
|
|
compatible = "ti,dra7-dsp-iommu";
|
|
reg = <0x41501000 0x100>;
|
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmu0_dsp2";
|
|
#iommu-cells = <0>;
|
|
ti,syscon-mmuconfig = <&dsp2_system 0x0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmu1_dsp2: mmu@41502000 {
|
|
compatible = "ti,dra7-dsp-iommu";
|
|
reg = <0x41502000 0x100>;
|
|
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmu1_dsp2";
|
|
#iommu-cells = <0>;
|
|
ti,syscon-mmuconfig = <&dsp2_system 0x1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
&cpu0_opp_table {
|
|
opp-shared;
|
|
};
|
|
|
|
&dss {
|
|
reg = <0x58000000 0x80>,
|
|
<0x58004054 0x4>,
|
|
<0x58004300 0x20>,
|
|
<0x58009054 0x4>,
|
|
<0x58009300 0x20>;
|
|
reg-names = "dss", "pll1_clkctrl", "pll1",
|
|
"pll2_clkctrl", "pll2";
|
|
|
|
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
|
|
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
|
|
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
|
|
clock-names = "fck", "video1_clk", "video2_clk";
|
|
};
|
|
|
|
&mailbox5 {
|
|
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
|
|
ti,mbox-tx = <6 2 2>;
|
|
ti,mbox-rx = <4 2 2>;
|
|
status = "disabled";
|
|
};
|
|
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
|
|
ti,mbox-tx = <5 2 2>;
|
|
ti,mbox-rx = <1 2 2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
&mailbox6 {
|
|
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
|
|
ti,mbox-tx = <6 2 2>;
|
|
ti,mbox-rx = <4 2 2>;
|
|
status = "disabled";
|
|
};
|
|
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
|
|
ti,mbox-tx = <5 2 2>;
|
|
ti,mbox-rx = <1 2 2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
&pcie1_rc {
|
|
compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
|
|
};
|
|
|
|
&pcie1_ep {
|
|
compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
|
|
};
|
|
|
|
&pcie2_rc {
|
|
compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
|
|
};
|