175 lines
4.1 KiB
Plaintext
175 lines
4.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
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*/
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#include <dt-bindings/clock/hi3519-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0>;
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};
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};
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gic: interrupt-controller@10300000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
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};
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clk_3m: clk_3m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <3000000>;
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};
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crg: clock-reset-controller@12010000 {
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compatible = "hisilicon,hi3519-crg";
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#clock-cells = <1>;
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#reset-cells = <2>;
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reg = <0x12010000 0x10000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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uart0: serial@12100000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12100000 0x1000>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_UART0_CLK>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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uart1: serial@12101000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12101000 0x1000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_UART1_CLK>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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uart2: serial@12102000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12102000 0x1000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_UART2_CLK>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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uart3: serial@12103000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12103000 0x1000>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_UART3_CLK>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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uart4: serial@12104000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12104000 0x1000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_UART4_CLK>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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dual_timer0: timer@12000000 {
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compatible = "arm,sp804", "arm,primecell";
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x12000000 0x1000>;
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clocks = <&clk_3m>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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dual_timer1: timer@12001000 {
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compatible = "arm,sp804", "arm,primecell";
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x12001000 0x1000>;
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clocks = <&clk_3m>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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dual_timer2: timer@12002000 {
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compatible = "arm,sp804", "arm,primecell";
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x12002000 0x1000>;
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clocks = <&clk_3m>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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spi_bus0: spi@12120000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x12120000 0x1000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_SPI0_CLK>;
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clock-names = "apb_pclk";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disable";
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};
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spi_bus1: spi@12121000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x12121000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_SPI1_CLK>;
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clock-names = "apb_pclk";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disable";
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};
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spi_bus2: spi@12122000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x12122000 0x1000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_SPI2_CLK>;
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clock-names = "apb_pclk";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disable";
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};
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sysctrl: system-controller@12020000 {
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compatible = "hisilicon,hi3519-sysctrl", "syscon";
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reg = <0x12020000 0x1000>;
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};
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reboot {
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compatible = "syscon-reboot";
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regmap = <&sysctrl>;
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offset = <0x4>;
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mask = <0xdeadbeef>;
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};
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};
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};
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