718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
425 lines
14 KiB
C
425 lines
14 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer. 2. The name
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* of the author may not be used to endorse or promote products derived from
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* this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the
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* 3c590 family.
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*/
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/*
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* Some global constants
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*/
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#define TX_INIT_RATE 16
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#define TX_INIT_MAX_RATE 64
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#define RX_INIT_LATENCY 64
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#define RX_INIT_EARLY_THRESH 64
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#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */
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#define MIN_RX_EARLY_THRESHL 4
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#define EEPROMSIZE 0x40
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#define MAX_EEPROMBUSY 1000
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#define VX_LAST_TAG 0xd7
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#define VX_MAX_BOARDS 16
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/*
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* Commands to read/write EEPROM trough EEPROM command register (Window 0,
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* Offset 0xa)
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*/
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#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
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#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
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#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
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#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
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#define EEPROM_BUSY (1<<15)
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#define EEPROM_TST_MODE (1<<14)
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/*
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* Some short functions, worth to let them be a macro
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*/
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#define GO_WINDOW(x) CSR_WRITE_2(sc, VX_COMMAND, WINDOW_SELECT|(x))
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/**************************************************************************
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* *
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* These define the EEPROM data structure. They are used in the probe
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* function to verify the existence of the adapter after having sent
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* the ID_Sequence.
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*
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**************************************************************************/
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#define EEPROM_NODE_ADDR_0 0x0 /* Word */
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#define EEPROM_NODE_ADDR_1 0x1 /* Word */
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#define EEPROM_NODE_ADDR_2 0x2 /* Word */
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#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
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#define EEPROM_MFG_DATE 0x4 /* Manufacturing date */
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#define EEPROM_MFG_DIVSION 0x5 /* Manufacturing division */
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#define EEPROM_MFG_PRODUCT 0x6 /* Product code */
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#define EEPROM_MFG_ID 0x7 /* 0x6d50 */
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#define EEPROM_ADDR_CFG 0x8 /* Base addr */
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#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
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#define EEPROM_OEM_ADDR0 0xa
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#define EEPROM_OEM_ADDR1 0xb
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#define EEPROM_OEM_ADDR2 0xc
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#define EEPROM_SOFTINFO 0xd
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#define EEPROM_COMPAT 0xe
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#define EEPROM_SOFTINFO2 0xf
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#define EEPROM_CAP 0x10
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#define EEPROM_INT_CONFIG_0 0x12
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#define EEPROM_INT_CONFIG_1 0x13
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/* RAM Partition TX FIFO/RX FIFO */
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#define ICW1_RAM_PART_MASK 0x03
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#define ICW1_RAM_PART_35 0x00 /* 2:5 (only legal if RAM size == 000b
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* default power-up/reset */
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#define ICW1_RAM_PART_13 0x01 /* 1:3 (only legal if RAM size ==
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* 000b) */
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#define ICW1_RAM_PART_11 0x10 /* 1:1 */
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#define ICW1_RAM_PART_RESV 0x11 /* Reserved */
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/* ISA Adapter Selection */
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#define ICW1_IAS_MASK 0x0c
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#define ICW1_IAS_DIS 0x00 /* Both mechanisms disabled (default) */
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#define ICW1_IAS_ISA 0x04 /* ISA contention only */
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#define ICW1_IAS_PNP 0x08 /* ISA Plug and Play only */
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#define ICW1_IAS_BOTH 0x0c /* Both mechanisms enabled */
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#define EEPROM_CHECKSUM_EL3 0x17
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#define NO_RX_OVN_ANOMALY (1<<5)
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/**************************************************************************
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* These are the registers for the 3Com 3c509 and their bit patterns when *
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* applicable. They have been taken out the "EtherLink III Parallel *
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* Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
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* from 3com. *
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**************************************************************************/
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#define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a
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* command reg. */
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#define VX_STATUS 0x0e /* Read. BASE+0x0e is always status
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* reg. */
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#define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window
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* reg. */
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/*
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* Window 0 registers. Setup.
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*/
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/* Write */
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#define VX_W0_EEPROM_DATA 0x0c
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#define VX_W0_EEPROM_COMMAND 0x0a
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#define VX_W0_RESOURCE_CFG 0x08
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#define VX_W0_ADDRESS_CFG 0x06
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#define VX_W0_CONFIG_CTRL 0x04
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/* Read */
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#define VX_W0_PRODUCT_ID 0x02
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#define VX_W0_MFG_ID 0x00
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/*
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* Window 1 registers. Operating Set.
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*/
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/* Write */
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#define VX_W1_TX_PIO_WR_2 0x02
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#define VX_W1_TX_PIO_WR_1 0x00
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/* Read */
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#define VX_W1_FREE_TX 0x0c
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#define VX_W1_TX_STATUS 0x0b /* byte */
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#define VX_W1_TIMER 0x0a /* byte */
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#define VX_W1_RX_STATUS 0x08
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#define VX_W1_RX_PIO_RD_2 0x02
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#define VX_W1_RX_PIO_RD_1 0x00
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/*
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* Window 2 registers. Station Address Setup/Read
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*/
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/* Read/Write */
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#define VX_W2_ADDR_5 0x05
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#define VX_W2_ADDR_4 0x04
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#define VX_W2_ADDR_3 0x03
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#define VX_W2_ADDR_2 0x02
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#define VX_W2_ADDR_1 0x01
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#define VX_W2_ADDR_0 0x00
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/*
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* Window 3 registers. FIFO Management.
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*/
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/* Read */
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#define VX_W3_INTERNAL_CFG 0x00
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#define VX_W3_RESET_OPT 0x08
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#define VX_W3_FREE_TX 0x0c
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#define VX_W3_FREE_RX 0x0a
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/*
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* Window 4 registers. Diagnostics.
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*/
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/* Read/Write */
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#define VX_W4_MEDIA_TYPE 0x0a
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#define VX_W4_CTRLR_STATUS 0x08
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#define VX_W4_NET_DIAG 0x06
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#define VX_W4_FIFO_DIAG 0x04
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#define VX_W4_HOST_DIAG 0x02
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#define VX_W4_TX_DIAG 0x00
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/*
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* Window 5 Registers. Results and Internal status.
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*/
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/* Read */
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#define VX_W5_READ_0_MASK 0x0c
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#define VX_W5_INTR_MASK 0x0a
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#define VX_W5_RX_FILTER 0x08
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#define VX_W5_RX_EARLY_THRESH 0x06
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#define VX_W5_TX_AVAIL_THRESH 0x02
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#define VX_W5_TX_START_THRESH 0x00
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/*
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* Window 6 registers. Statistics.
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*/
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/* Read/Write */
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#define TX_TOTAL_OK 0x0c
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#define RX_TOTAL_OK 0x0a
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#define TX_DEFERRALS 0x08
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#define RX_FRAMES_OK 0x07
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#define TX_FRAMES_OK 0x06
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#define RX_OVERRUNS 0x05
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#define TX_COLLISIONS 0x04
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#define TX_AFTER_1_COLLISION 0x03
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#define TX_AFTER_X_COLLISIONS 0x02
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#define TX_NO_SQE 0x01
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#define TX_CD_LOST 0x00
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/****************************************
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*
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* Register definitions.
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*
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****************************************/
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/*
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* Command register. All windows.
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*
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* 16 bit register.
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* 15-11: 5-bit code for command to be executed.
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* 10-0: 11-bit arg if any. For commands with no args;
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* this can be set to anything.
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*/
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#define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms
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* after issuing */
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#define WINDOW_SELECT (u_short) (0x1<<11)
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#define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to
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* determine whether
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* this is needed. If
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* so; wait 800 uSec
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* before using trans-
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* ceiver. */
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#define RX_DISABLE (u_short) (0x3<<11) /* state disabled on
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* power-up */
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#define RX_ENABLE (u_short) (0x4<<11)
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#define RX_RESET (u_short) (0x5<<11)
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#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11)
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#define TX_ENABLE (u_short) (0x9<<11)
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#define TX_DISABLE (u_short) (0xa<<11)
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#define TX_RESET (u_short) (0xb<<11)
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#define REQ_INTR (u_short) (0xc<<11)
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/*
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* The following C_* acknowledge the various interrupts.
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* Some of them don't do anything. See the manual.
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*/
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#define ACK_INTR (u_short) (0x6800)
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#define C_INTR_LATCH (u_short) (ACK_INTR|0x1)
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#define C_CARD_FAILURE (u_short) (ACK_INTR|0x2)
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#define C_TX_COMPLETE (u_short) (ACK_INTR|0x4)
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#define C_TX_AVAIL (u_short) (ACK_INTR|0x8)
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#define C_RX_COMPLETE (u_short) (ACK_INTR|0x10)
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#define C_RX_EARLY (u_short) (ACK_INTR|0x20)
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#define C_INT_RQD (u_short) (ACK_INTR|0x40)
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#define C_UPD_STATS (u_short) (ACK_INTR|0x80)
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#define SET_INTR_MASK (u_short) (0xe<<11)
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#define SET_RD_0_MASK (u_short) (0xf<<11)
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#define SET_RX_FILTER (u_short) (0x10<<11)
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#define FIL_INDIVIDUAL (u_short) (0x1)
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#define FIL_MULTICAST (u_short) (0x02)
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#define FIL_BRDCST (u_short) (0x04)
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#define FIL_PROMISC (u_short) (0x08)
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#define SET_RX_EARLY_THRESH (u_short) (0x11<<11)
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#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11)
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#define SET_TX_START_THRESH (u_short) (0x13<<11)
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#define STATS_ENABLE (u_short) (0x15<<11)
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#define STATS_DISABLE (u_short) (0x16<<11)
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#define STOP_TRANSCEIVER (u_short) (0x17<<11)
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/*
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* Status register. All windows.
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*
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* 15-13: Window number(0-7).
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* 12: Command_in_progress.
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* 11: reserved.
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* 10: reserved.
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* 9: reserved.
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* 8: reserved.
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* 7: Update Statistics.
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* 6: Interrupt Requested.
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* 5: RX Early.
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* 4: RX Complete.
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* 3: TX Available.
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* 2: TX Complete.
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* 1: Adapter Failure.
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* 0: Interrupt Latch.
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*/
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#define S_INTR_LATCH (u_short) (0x1)
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#define S_CARD_FAILURE (u_short) (0x2)
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#define S_TX_COMPLETE (u_short) (0x4)
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#define S_TX_AVAIL (u_short) (0x8)
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#define S_RX_COMPLETE (u_short) (0x10)
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#define S_RX_EARLY (u_short) (0x20)
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#define S_INT_RQD (u_short) (0x40)
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#define S_UPD_STATS (u_short) (0x80)
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#define S_COMMAND_IN_PROGRESS (u_short) (0x1000)
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#define VX_BUSY_WAIT while (CSR_READ_2(sc, VX_STATUS) & S_COMMAND_IN_PROGRESS)
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/* Address Config. Register.
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* Window 0/Port 06
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*/
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#define ACF_CONNECTOR_BITS 14
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#define ACF_CONNECTOR_UTP 0
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#define ACF_CONNECTOR_AUI 1
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#define ACF_CONNECTOR_BNC 3
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#define INTERNAL_CONNECTOR_BITS 20
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#define INTERNAL_CONNECTOR_MASK 0x01700000
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/*
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* FIFO Registers. RX Status.
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*
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* 15: Incomplete or FIFO empty.
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* 14: 1: Error in RX Packet 0: Incomplete or no error.
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* 13-11: Type of error.
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* 1000 = Overrun.
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* 1011 = Run Packet Error.
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* 1100 = Alignment Error.
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* 1101 = CRC Error.
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* 1001 = Oversize Packet Error (>1514 bytes)
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* 0010 = Dribble Bits.
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* (all other error codes, no errors.)
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*
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* 10-0: RX Bytes (0-1514)
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*/
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#define ERR_INCOMPLETE (u_short) (0x8000)
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#define ERR_RX (u_short) (0x4000)
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#define ERR_MASK (u_short) (0x7800)
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#define ERR_OVERRUN (u_short) (0x4000)
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#define ERR_RUNT (u_short) (0x5800)
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#define ERR_ALIGNMENT (u_short) (0x6000)
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#define ERR_CRC (u_short) (0x6800)
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#define ERR_OVERSIZE (u_short) (0x4800)
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#define ERR_DRIBBLE (u_short) (0x1000)
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/*
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* TX Status.
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*
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* Reports the transmit status of a completed transmission. Writing this
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* register pops the transmit completion stack.
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*
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* Window 1/Port 0x0b.
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*
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* 7: Complete
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* 6: Interrupt on successful transmission requested.
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* 5: Jabber Error (TP Only, TX Reset required. )
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* 4: Underrun (TX Reset required. )
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* 3: Maximum Collisions.
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* 2: TX Status Overflow.
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* 1-0: Undefined.
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*
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*/
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#define TXS_COMPLETE 0x80
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#define TXS_INTR_REQ 0x40
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#define TXS_JABBER 0x20
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#define TXS_UNDERRUN 0x10
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#define TXS_MAX_COLLISION 0x8
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#define TXS_STATUS_OVERFLOW 0x4
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#define RS_AUI (1<<5)
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#define RS_BNC (1<<4)
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#define RS_UTP (1<<3)
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#define RS_T4 (1<<0)
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#define RS_TX (1<<1)
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#define RS_FX (1<<2)
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#define RS_MII (1<<6)
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/*
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* FIFO Status (Window 4)
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*
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* Supports FIFO diagnostics
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*
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* Window 4/Port 0x04.1
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*
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* 15: 1=RX receiving (RO). Set when a packet is being received
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* into the RX FIFO.
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* 14: Reserved
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* 13: 1=RX underrun (RO). Generates Adapter Failure interrupt.
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* Requires RX Reset or Global Reset command to recover.
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* It is generated when you read past the end of a packet -
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* reading past what has been received so far will give bad
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* data.
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* 12: 1=RX status overrun (RO). Set when there are already 8
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* packets in the RX FIFO. While this bit is set, no additional
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* packets are received. Requires no action on the part of
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* the host. The condition is cleared once a packet has been
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* read out of the RX FIFO.
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* 11: 1=RX overrun (RO). Set when the RX FIFO is full (there
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* may not be an overrun packet yet). While this bit is set,
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* no additional packets will be received (some additional
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* bytes can still be pending between the wire and the RX
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* FIFO). Requires no action on the part of the host. The
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* condition is cleared once a few bytes have been read out
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* from the RX FIFO.
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* 10: 1=TX overrun (RO). Generates adapter failure interrupt.
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* Requires TX Reset or Global Reset command to recover.
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* Disables Transmitter.
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* 9-8: Unassigned.
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* 7-0: Built in self test bits for the RX and TX FIFO's.
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*/
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#define FIFOS_RX_RECEIVING (u_short) 0x8000
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#define FIFOS_RX_UNDERRUN (u_short) 0x2000
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#define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000
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#define FIFOS_RX_OVERRUN (u_short) 0x0800
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#define FIFOS_TX_OVERRUN (u_short) 0x0400
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/*
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* Misc defines for various things.
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*/
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#define TAG_ADAPTER 0xd0
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#define ACTIVATE_ADAPTER_TO_CONFIG 0xff
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#define ENABLE_DRQ_IRQ 0x0001
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#define MFG_ID 0x506d /* `TCM' */
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#define PROD_ID 0x5090
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#define JABBER_GUARD_ENABLE 0x40
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#define LINKBEAT_ENABLE 0x80
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#define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE)
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#define DISABLE_UTP 0x0
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#define RX_BYTES_MASK (u_short) (0x07ff)
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#define TX_INDICATE (1<<15)
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#define VX_IOSIZE 0x20
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#define VX_CONNECTORS 8
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