1251a82da6
detection pins to the Marvell Xenon SDHCI controller. These features are enable by 'vqmmc-supply' and 'cd-gpios' properties in the DTS. This fixes the SD Card detection on espressobin. Sponsored by: Rubicon Communications, LLC (Netgate)
640 lines
17 KiB
C
640 lines
17 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Marvell Xenon SDHCI controller driver.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/extres/regulator/regulator.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/mmc/bridge.h>
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#include <dev/mmc/mmcbrvar.h>
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#include <dev/mmc/mmcreg.h>
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#include <dev/sdhci/sdhci.h>
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#include <dev/sdhci/sdhci_fdt_gpio.h>
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#include <dev/sdhci/sdhci_xenon.h>
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#include "mmcbr_if.h"
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#include "sdhci_if.h"
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#include "opt_mmccam.h"
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#include "opt_soc.h"
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#define MAX_SLOTS 6
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static struct ofw_compat_data compat_data[] = {
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{ "marvell,armada-3700-sdhci", 1 },
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#ifdef SOC_MARVELL_8K
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{ "marvell,armada-cp110-sdhci", 1 },
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{ "marvell,armada-ap806-sdhci", 1 },
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#endif
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{ NULL, 0 }
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};
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struct sdhci_xenon_softc {
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device_t dev; /* Controller device */
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int slot_id; /* Controller ID */
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phandle_t node; /* FDT node */
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uint32_t quirks; /* Chip specific quirks */
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uint32_t caps; /* If we override SDHCI_CAPABILITIES */
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uint32_t max_clk; /* Max possible freq */
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struct resource *irq_res; /* IRQ resource */
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void *intrhand; /* Interrupt handle */
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struct sdhci_fdt_gpio *gpio; /* GPIO pins for CD detection. */
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struct sdhci_slot *slot; /* SDHCI internal data */
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struct resource *mem_res; /* Memory resource */
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regulator_t reg_vqmmc; /* vqmmc-supply regulator */
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uint8_t znr; /* PHY ZNR */
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uint8_t zpr; /* PHY ZPR */
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bool no_18v; /* No 1.8V support */
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bool slow_mode; /* PHY slow mode */
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bool wp_inverted; /* WP pin is inverted */
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};
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static uint8_t
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sdhci_xenon_read_1(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off)
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{
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struct sdhci_xenon_softc *sc = device_get_softc(dev);
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return (bus_read_1(sc->mem_res, off));
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}
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static void
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sdhci_xenon_write_1(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint8_t val)
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{
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struct sdhci_xenon_softc *sc = device_get_softc(dev);
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bus_write_1(sc->mem_res, off, val);
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}
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static uint16_t
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sdhci_xenon_read_2(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off)
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{
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struct sdhci_xenon_softc *sc = device_get_softc(dev);
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return (bus_read_2(sc->mem_res, off));
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}
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static void
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sdhci_xenon_write_2(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint16_t val)
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{
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struct sdhci_xenon_softc *sc = device_get_softc(dev);
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bus_write_2(sc->mem_res, off, val);
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}
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static uint32_t
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sdhci_xenon_read_4(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off)
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{
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struct sdhci_xenon_softc *sc = device_get_softc(dev);
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uint32_t val32;
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val32 = bus_read_4(sc->mem_res, off);
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if (off == SDHCI_CAPABILITIES && sc->no_18v)
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val32 &= ~SDHCI_CAN_VDD_180;
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return (val32);
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}
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static void
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sdhci_xenon_write_4(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint32_t val)
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{
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struct sdhci_xenon_softc *sc = device_get_softc(dev);
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bus_write_4(sc->mem_res, off, val);
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}
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static void
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sdhci_xenon_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint32_t *data, bus_size_t count)
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{
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struct sdhci_xenon_softc *sc = device_get_softc(dev);
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bus_read_multi_4(sc->mem_res, off, data, count);
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}
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static void
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sdhci_xenon_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint32_t *data, bus_size_t count)
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{
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struct sdhci_xenon_softc *sc = device_get_softc(dev);
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bus_write_multi_4(sc->mem_res, off, data, count);
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}
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static void
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sdhci_xenon_intr(void *arg)
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{
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struct sdhci_xenon_softc *sc = (struct sdhci_xenon_softc *)arg;
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sdhci_generic_intr(sc->slot);
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}
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static int
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sdhci_xenon_get_ro(device_t bus, device_t dev)
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{
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struct sdhci_xenon_softc *sc = device_get_softc(bus);
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return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted);
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}
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static bool
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sdhci_xenon_get_card_present(device_t dev, struct sdhci_slot *slot)
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{
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struct sdhci_xenon_softc *sc = device_get_softc(dev);
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return (sdhci_fdt_gpio_get_present(sc->gpio));
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}
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static int
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sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios)
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{
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int i;
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struct sdhci_xenon_softc *sc;
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uint32_t reg;
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sc = device_get_softc(brdev);
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reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
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reg |= XENON_SAMPL_INV_QSP_PHASE_SELECT;
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switch (ios->timing) {
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case bus_timing_normal:
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case bus_timing_hs:
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case bus_timing_uhs_sdr12:
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case bus_timing_uhs_sdr25:
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case bus_timing_uhs_sdr50:
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reg |= XENON_TIMING_ADJUST_SLOW_MODE;
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break;
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default:
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reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
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}
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if (sc->slow_mode)
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reg |= XENON_TIMING_ADJUST_SLOW_MODE;
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bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
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reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
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reg |= XENON_PHY_INITIALIZATION;
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bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
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/* Wait for the eMMC PHY init. */
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for (i = 100; i > 0; i--) {
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DELAY(100);
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reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
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if ((reg & XENON_PHY_INITIALIZATION) == 0)
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break;
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}
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if (i == 0) {
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device_printf(brdev, "eMMC PHY failed to initialize\n");
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return (ETIMEDOUT);
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}
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return (0);
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}
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static int
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sdhci_xenon_phy_set(device_t brdev, struct mmc_ios *ios)
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{
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struct sdhci_xenon_softc *sc;
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uint32_t reg;
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sc = device_get_softc(brdev);
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/* Setup pad, set bit[28] and bits[26:24] */
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reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL);
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reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
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XENON_FC_QSP_RECEN | XENON_OEN_QSN);
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/* All FC_XX_RECEIVCE should be set as CMOS Type */
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reg |= XENON_FC_ALL_CMOS_RECEIVER;
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bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg);
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/* Set CMD and DQ Pull Up */
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reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);
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reg |= (XENON_EMMC_FC_CMD_PU | XENON_EMMC_FC_DQ_PU);
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reg &= ~(XENON_EMMC_FC_CMD_PD | XENON_EMMC_FC_DQ_PD);
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bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);
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if (ios->timing == bus_timing_normal)
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return (sdhci_xenon_phy_init(brdev, ios));
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/* Clear SDIO mode, no SDIO support for now. */
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reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
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reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
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bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
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/*
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* Set preferred ZNR and ZPR value.
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* The ZNR and ZPR value vary between different boards.
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* Define them both in the DTS for the board!
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*/
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reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2);
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reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
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reg |= ((sc->znr << XENON_ZNR_SHIFT) | sc->zpr);
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bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg);
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/* Disable the SD clock to set EMMC_PHY_FUNC_CONTROL. */
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reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);
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reg &= ~SDHCI_CLOCK_CARD_EN;
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bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);
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reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL);
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switch (ios->timing) {
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case bus_timing_mmc_hs400:
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reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
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XENON_CMD_DDR_MODE;
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reg &= ~XENON_DQ_ASYNC_MODE;
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break;
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case bus_timing_uhs_ddr50:
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case bus_timing_mmc_ddr52:
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reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
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XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE;
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break;
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default:
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reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
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XENON_CMD_DDR_MODE);
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reg |= XENON_DQ_ASYNC_MODE;
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}
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bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg);
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/* Enable SD clock. */
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reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);
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reg |= SDHCI_CLOCK_CARD_EN;
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bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);
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if (ios->timing == bus_timing_mmc_hs400)
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bus_write_4(sc->mem_res, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
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XENON_LOGIC_TIMING_VALUE);
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else {
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/* Disable both SDHC Data Strobe and Enhanced Strobe. */
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reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL);
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reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE);
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bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg);
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/* Clear Strobe line Pull down or Pull up. */
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reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);
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reg &= ~(XENON_EMMC_FC_QSP_PD | XENON_EMMC_FC_QSP_PU);
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bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);
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}
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return (sdhci_xenon_phy_init(brdev, ios));
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}
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static int
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sdhci_xenon_update_ios(device_t brdev, device_t reqdev)
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{
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int err;
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struct sdhci_xenon_softc *sc;
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struct mmc_ios *ios;
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struct sdhci_slot *slot;
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uint32_t reg;
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err = sdhci_generic_update_ios(brdev, reqdev);
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if (err != 0)
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return (err);
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sc = device_get_softc(brdev);
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slot = device_get_ivars(reqdev);
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ios = &slot->host.ios;
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switch (ios->power_mode) {
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case power_on:
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break;
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case power_off:
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if (bootverbose)
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device_printf(sc->dev, "Powering down sd/mmc\n");
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if (sc->reg_vqmmc)
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regulator_disable(sc->reg_vqmmc);
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break;
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case power_up:
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if (bootverbose)
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device_printf(sc->dev, "Powering up sd/mmc\n");
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if (sc->reg_vqmmc)
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regulator_enable(sc->reg_vqmmc);
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break;
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};
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/* Update the PHY settings. */
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if (ios->clock != 0)
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sdhci_xenon_phy_set(brdev, ios);
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if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) {
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/* Enable SDCLK_IDLEOFF. */
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reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
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reg |= 1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id);
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bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
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}
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return (0);
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}
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static int
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sdhci_xenon_switch_vccq(device_t brdev, device_t reqdev)
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{
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struct sdhci_xenon_softc *sc;
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struct sdhci_slot *slot;
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int uvolt, err;
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sc = device_get_softc(brdev);
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if (sc->reg_vqmmc == NULL)
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return EOPNOTSUPP;
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slot = device_get_ivars(reqdev);
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switch (slot->host.ios.vccq) {
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case vccq_180:
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uvolt = 1800000;
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break;
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case vccq_330:
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uvolt = 3300000;
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break;
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default:
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return EINVAL;
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}
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err = regulator_set_voltage(sc->reg_vqmmc, uvolt, uvolt);
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if (err != 0) {
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device_printf(sc->dev,
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"Cannot set vqmmc to %d<->%d\n",
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uvolt,
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uvolt);
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return (err);
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}
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return (0);
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}
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static int
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sdhci_xenon_probe(device_t dev)
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{
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struct sdhci_xenon_softc *sc = device_get_softc(dev);
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pcell_t cid;
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sc->quirks = 0;
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sc->slot_id = 0;
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sc->max_clk = XENON_MMC_MAX_CLK;
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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sc->node = ofw_bus_get_node(dev);
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device_set_desc(dev, "Armada Xenon SDHCI controller");
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/* Allow dts to patch quirks, slots, and max-frequency. */
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if ((OF_getencprop(sc->node, "quirks", &cid, sizeof(cid))) > 0)
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sc->quirks = cid;
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if ((OF_getencprop(sc->node, "max-frequency", &cid, sizeof(cid))) > 0)
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sc->max_clk = cid;
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if (OF_hasprop(sc->node, "no-1-8-v"))
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sc->no_18v = true;
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if (OF_hasprop(sc->node, "wp-inverted"))
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sc->wp_inverted = true;
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if (OF_hasprop(sc->node, "marvell,xenon-phy-slow-mode"))
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sc->slow_mode = true;
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|
sc->znr = XENON_ZNR_DEF_VALUE;
|
|
if ((OF_getencprop(sc->node, "marvell,xenon-phy-znr", &cid,
|
|
sizeof(cid))) > 0)
|
|
sc->znr = cid & XENON_ZNR_MASK;
|
|
sc->zpr = XENON_ZPR_DEF_VALUE;
|
|
if ((OF_getencprop(sc->node, "marvell,xenon-phy-zpr", &cid,
|
|
sizeof(cid))) > 0)
|
|
sc->zpr = cid & XENON_ZPR_MASK;
|
|
if (regulator_get_by_ofw_property(dev, 0, "vqmmc-supply",
|
|
&sc->reg_vqmmc) == 0 && bootverbose) {
|
|
if (bootverbose)
|
|
device_printf(dev, "vqmmc-supply regulator found\n");
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
sdhci_xenon_attach(device_t dev)
|
|
{
|
|
struct sdhci_xenon_softc *sc = device_get_softc(dev);
|
|
struct sdhci_slot *slot;
|
|
int err, rid;
|
|
uint32_t reg;
|
|
|
|
sc->dev = dev;
|
|
|
|
/* Allocate IRQ. */
|
|
rid = 0;
|
|
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->irq_res == NULL) {
|
|
device_printf(dev, "Can't allocate IRQ\n");
|
|
return (ENOMEM);
|
|
}
|
|
|
|
/* Allocate memory. */
|
|
rid = 0;
|
|
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
&rid, RF_ACTIVE);
|
|
if (sc->mem_res == NULL) {
|
|
bus_release_resource(dev, SYS_RES_IRQ,
|
|
rman_get_rid(sc->irq_res), sc->irq_res);
|
|
device_printf(dev, "Can't allocate memory for slot\n");
|
|
return (ENOMEM);
|
|
}
|
|
|
|
slot = malloc(sizeof(*slot), M_DEVBUF, M_ZERO | M_WAITOK);
|
|
|
|
/* Check if the device is flagged as non-removable. */
|
|
if (OF_hasprop(sc->node, "non-removable")) {
|
|
slot->opt |= SDHCI_NON_REMOVABLE;
|
|
if (bootverbose)
|
|
device_printf(dev, "Non-removable media\n");
|
|
}
|
|
|
|
slot->quirks = sc->quirks;
|
|
slot->caps = sc->caps;
|
|
slot->max_clk = sc->max_clk;
|
|
sc->slot = slot;
|
|
|
|
/*
|
|
* Set up any gpio pin handling described in the FDT data. This cannot
|
|
* fail; see comments in sdhci_fdt_gpio.h for details.
|
|
*/
|
|
sc->gpio = sdhci_fdt_gpio_setup(dev, slot);
|
|
|
|
if (sdhci_init_slot(dev, sc->slot, 0))
|
|
goto fail;
|
|
|
|
/* Activate the interrupt */
|
|
err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
|
|
NULL, sdhci_xenon_intr, sc, &sc->intrhand);
|
|
if (err) {
|
|
device_printf(dev, "Cannot setup IRQ\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* Disable Auto Clock Gating. */
|
|
reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
|
|
reg |= XENON_AUTO_CLKGATE_DISABLE;
|
|
bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
|
|
|
|
/* Enable this SD controller. */
|
|
reg |= (1 << sc->slot_id);
|
|
bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
|
|
|
|
/* Enable Parallel Transfer. */
|
|
reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);
|
|
reg |= (1 << sc->slot_id);
|
|
bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);
|
|
|
|
/* Enable Auto Clock Gating. */
|
|
reg &= ~XENON_AUTO_CLKGATE_DISABLE;
|
|
bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
|
|
|
|
/* Disable SDCLK_IDLEOFF before the card initialization. */
|
|
reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
|
|
reg &= ~(1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id));
|
|
bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
|
|
|
|
/* Mask command conflict errors. */
|
|
reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);
|
|
reg |= XENON_MASK_CMD_CONFLICT_ERR;
|
|
bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);
|
|
|
|
/* Process cards detection. */
|
|
sdhci_start_slot(sc->slot);
|
|
|
|
return (0);
|
|
|
|
fail:
|
|
bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
|
|
sc->irq_res);
|
|
bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res),
|
|
sc->mem_res);
|
|
free(sc->slot, M_DEVBUF);
|
|
sc->slot = NULL;
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
sdhci_xenon_detach(device_t dev)
|
|
{
|
|
struct sdhci_xenon_softc *sc = device_get_softc(dev);
|
|
|
|
if (sc->gpio != NULL)
|
|
sdhci_fdt_gpio_teardown(sc->gpio);
|
|
|
|
bus_generic_detach(dev);
|
|
bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
|
|
bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
|
|
sc->irq_res);
|
|
sdhci_cleanup_slot(sc->slot);
|
|
bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res),
|
|
sc->mem_res);
|
|
free(sc->slot, M_DEVBUF);
|
|
sc->slot = NULL;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t sdhci_xenon_methods[] = {
|
|
/* device_if */
|
|
DEVMETHOD(device_probe, sdhci_xenon_probe),
|
|
DEVMETHOD(device_attach, sdhci_xenon_attach),
|
|
DEVMETHOD(device_detach, sdhci_xenon_detach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
|
|
|
|
/* mmcbr_if */
|
|
DEVMETHOD(mmcbr_update_ios, sdhci_xenon_update_ios),
|
|
DEVMETHOD(mmcbr_request, sdhci_generic_request),
|
|
DEVMETHOD(mmcbr_get_ro, sdhci_xenon_get_ro),
|
|
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
|
|
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
|
|
DEVMETHOD(mmcbr_switch_vccq, sdhci_xenon_switch_vccq),
|
|
|
|
/* SDHCI registers accessors */
|
|
DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1),
|
|
DEVMETHOD(sdhci_read_2, sdhci_xenon_read_2),
|
|
DEVMETHOD(sdhci_read_4, sdhci_xenon_read_4),
|
|
DEVMETHOD(sdhci_read_multi_4, sdhci_xenon_read_multi_4),
|
|
DEVMETHOD(sdhci_write_1, sdhci_xenon_write_1),
|
|
DEVMETHOD(sdhci_write_2, sdhci_xenon_write_2),
|
|
DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4),
|
|
DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4),
|
|
DEVMETHOD(sdhci_get_card_present, sdhci_xenon_get_card_present),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t sdhci_xenon_driver = {
|
|
"sdhci_xenon",
|
|
sdhci_xenon_methods,
|
|
sizeof(struct sdhci_xenon_softc),
|
|
};
|
|
static devclass_t sdhci_xenon_devclass;
|
|
|
|
DRIVER_MODULE(sdhci_xenon, simplebus, sdhci_xenon_driver, sdhci_xenon_devclass,
|
|
NULL, NULL);
|
|
|
|
SDHCI_DEPEND(sdhci_xenon);
|
|
#ifndef MMCCAM
|
|
MMC_DECLARE_BRIDGE(sdhci_xenon);
|
|
#endif
|