d5d4261f35
The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
121 lines
3.5 KiB
C
121 lines
3.5 KiB
C
/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD
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* $FreeBSD$
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*/
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#ifndef __NLM_XLP_H__
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#define __NLM_XLP_H__
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/iomap.h>
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#define PIC_UART_0_IRQ 9
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#define PIC_PCIE_0_IRQ 11
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#define PIC_PCIE_1_IRQ 12
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#define PIC_PCIE_2_IRQ 13
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#define PIC_PCIE_3_IRQ 14
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#define PIC_EHCI_0_IRQ 16
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#define PIC_MMC_IRQ 21
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/* 41 used by IRQ_SMP */
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/* XLP 8xx/4xx A0, A1, A2 CPU COP0 PRIDs */
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#define CHIP_PROCESSOR_ID_XLP_8XX 0x10
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#define CHIP_PROCESSOR_ID_XLP_3XX 0x11
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#define CHIP_PROCESSOR_ID_XLP_416 0x94
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#define CHIP_PROCESSOR_ID_XLP_432 0x14
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/* Revision id's */
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#define XLP_REVISION_A0 0x00
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#define XLP_REVISION_A1 0x01
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#define XLP_REVISION_A2 0x02
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#define XLP_REVISION_B0 0x03
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#ifndef LOCORE
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/*
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* FreeBSD can be started with few threads and cores turned off,
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* so have a hardware thread id to FreeBSD cpuid mapping.
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*/
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extern int xlp_ncores;
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extern int xlp_threads_per_core;
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extern uint32_t xlp_hw_thread_mask;
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extern int xlp_cpuid_to_hwtid[];
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extern int xlp_hwtid_to_cpuid[];
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#ifdef SMP
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extern void xlp_enable_threads(int code);
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#endif
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uint32_t xlp_get_cpu_frequency(int node, int core);
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int nlm_set_device_frequency(int node, int devtype, int frequency);
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int xlp_irt_to_irq(int irt);
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int xlp_irq_to_irt(int irq);
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static __inline int nlm_processor_id(void)
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{
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return ((mips_rd_prid() >> 8) & 0xff);
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}
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static __inline int nlm_is_xlp3xx(void)
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{
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return (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_3XX);
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}
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static __inline int nlm_is_xlp4xx(void)
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{
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int prid = nlm_processor_id();
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return (prid == CHIP_PROCESSOR_ID_XLP_432 ||
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prid == CHIP_PROCESSOR_ID_XLP_416);
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}
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static __inline int nlm_is_xlp8xx(void)
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{
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int prid = nlm_processor_id();
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return (prid == CHIP_PROCESSOR_ID_XLP_8XX ||
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prid == CHIP_PROCESSOR_ID_XLP_432 ||
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prid == CHIP_PROCESSOR_ID_XLP_416);
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}
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static __inline int nlm_is_xlp8xx_ax(void)
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{
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uint32_t procid = mips_rd_prid();
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int prid = (procid >> 8) & 0xff;
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int rev = procid & 0xff;
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return ((prid == CHIP_PROCESSOR_ID_XLP_8XX ||
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prid == CHIP_PROCESSOR_ID_XLP_432 ||
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prid == CHIP_PROCESSOR_ID_XLP_416) &&
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(rev < XLP_REVISION_B0));
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}
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#endif /* LOCORE */
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#endif /* __NLM_XLP_H__ */
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