176 lines
8.1 KiB
C
176 lines
8.1 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_IF_ATEREG_H
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#define ARM_AT91_IF_ATEREG_H
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#define ETH_CTL 0x00 /* EMAC Control Register */
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#define ETH_CFG 0x04 /* EMAC Configuration Register */
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#define ETH_SR 0x08 /* EMAC STatus Register */
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#define ETH_TAR 0x0c /* EMAC Transmit Address Register */
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#define ETH_TCR 0x10 /* EMAC Transmit Control Register */
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#define ETH_TSR 0x14 /* EMAC Transmit Status Register */
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#define ETH_RBQP 0x18 /* EMAC Receive Buffer Queue Pointer */
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/* 0x1c reserved */
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#define ETH_RSR 0x20 /* EMAC Receive Status Register */
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#define ETH_ISR 0x24 /* EMAC Interrupt Status Register */
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#define ETH_IER 0x28 /* EMAC Interrupt Enable Register */
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#define ETH_IDR 0x2c /* EMAC Interrupt Disable Register */
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#define ETH_IMR 0x30 /* EMAC Interrupt Mask Register */
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#define ETH_MAN 0x34 /* EMAC PHY Maintenance Register */
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/* 0x38 reserved */
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/* 0x3c reserved */
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#define ETH_FRA 0x40 /* Frames Transmitted OK Register */
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#define ETH_SCOL 0x44 /* Single Collision Frame Register */
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#define ETH_MCOL 0x48 /* Multiple Collision Frame Register */
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#define ETH_OK 0x4c /* Frames Received OK Register */
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#define ETH_SEQE 0x50 /* Frame Check Sequence Error Reg */
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#define ETH_ALE 0x54 /* Alignment Error Register */
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#define ETH_DTE 0x58 /* Deferred Transmittion Frame Reg */
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#define ETH_LCOL 0x5c /* Late Collision Register */
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#define ETH_ECOL 0x60 /* Excessive Collision Register */
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#define ETH_TUE 0x64 /* Transmit Underrun Error Register */
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#define ETH_CSE 0x68 /* Carrier Sense Error Register */
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#define ETH_DRFC 0x6c /* Discarded RX Frame Register */
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#define ETH_ROV 0x68 /* Receive Overrun Register */
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#define ETH_CDE 0x64 /* Code Error Register */
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#define ETH_ELR 0x78 /* Excessive Length Error Register */
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#define ETH_RJB 0x7c /* Receive Jabber Register */
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#define ETH_USF 0x80 /* Undersize Frame Register */
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#define ETH_SQEE 0x84 /* SQE Test Error Register */
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/* 0x88 reserved */
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/* 0x8c reserved */
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#define ETH_HSL 0x90 /* EMAC Hash Address Low [31:0] */
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#define ETH_HSH 0x94 /* EMAC Hash Address High [63:32] */
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#define ETH_SA1L 0x98 /* EMAC Specific Address 1 Low */
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#define ETH_SA1H 0x9c /* EMAC Specific Address 1 High */
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#define ETH_SA2L 0xa0 /* EMAC Specific Address 2 Low */
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#define ETH_SA2H 0xa4 /* EMAC Specific Address 2 High */
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#define ETH_SA3L 0xa8 /* EMAC Specific Address 3 Low */
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#define ETH_SA3H 0xac /* EMAC Specific Address 3 High */
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#define ETH_SA4L 0xb0 /* EMAC Specific Address 4 Low */
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#define ETH_SA4H 0xb4 /* EMAC Specific Address 4 High */
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/* ETH_CTL */
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#define ETH_CTL_LB (1U << 0) /* LB: Loopback */
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#define ETH_CTL_LBL (1U << 1) /* LBL: Loopback Local */
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#define ETH_CTL_RE (1U << 2) /* RE: Receive Enable */
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#define ETH_CTL_TE (1U << 3) /* TE: Transmit Enable */
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#define ETH_CTL_MPE (1U << 4) /* MPE: Management Port Enable */
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#define ETH_CTL_CSR (1U << 5) /* CSR: Clear Statistics Registers */
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#define ETH_CTL_ISR (1U << 6) /* ISR: Incremenet Statistics Regs */
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#define ETH_CTL_WES (1U << 7) /* WES: Write Enable Statistics regs */
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#define ETH_CTL_BP (1U << 8) /* BP: Back Pressure */
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/* ETH_CFG */
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#define ETH_CFG_SPD (1U << 0) /* SPD: Speed 1 == 100: 0 == 10 */
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#define ETH_CFG_FD (1U << 1) /* FD: Full duplex */
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#define ETH_CFG_BR (1U << 2) /* BR: Bit Rate (optional?) */
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/* bit 3 reserved */
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#define ETH_CFG_CAF (1U << 4) /* CAF: Copy All Frames */
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#define ETH_CFG_NBC (1U << 5) /* NBC: No Broadcast */
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#define ETH_CFG_MTI (1U << 6) /* MTI: Multicast Hash Enable */
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#define ETH_CFG_UNI (1U << 7) /* UNI: Unicast Hash Enable */
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#define ETH_CFG_BIG (1U << 8) /* BIG: Receive 1522 Bytes */
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#define ETH_CFG_EAE (1U << 9) /* EAE: External Address Match En */
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#define ETH_CFG_CLK_8 (0U << 10) /* CLK: Clock / 8 */
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#define ETH_CFG_CLK_16 (1U << 10) /* CLK: Clock / 16 */
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#define ETH_CFG_CLK_32 (2U << 10) /* CLK: Clock / 32 */
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#define ETH_CFG_CLK_64 (3U << 10) /* CLK: Clock / 64 */
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#define ETH_CFG_RTY (1U << 12) /* RTY: Retry Test*/
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#define ETH_CFG_RMII (1U << 13) /* RMII: Reduce MII */
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/* ETH_SR */
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#define ETH_SR_LINK (1U << 0) /* Reserved! */
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#define ETH_SR_MDIO (1U << 1) /* MDIO pin status */
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#define ETH_SR_IDLE (1U << 2) /* IDLE (PHY logic) */
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/* ETH_TCR */
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#define ETH_TCR_NCRC (1U << 15) /* NCRC: No CRC */
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/* ETH_TSR */
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#define ETH_TSR_OVR (1U << 0) /* OVR: Ethernet Transmit Overrun */
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#define ETH_TSR_COL (1U << 1) /* COL: Collision Occurred */
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#define ETH_TSR_RLE (1U << 2) /* RLE: Retry Limit Exceeded */
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#define ETH_TSR_IDLE (1U << 3) /* IDLE: Transmitter Idle */
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#define ETH_TSR_BNQ (1U << 4) /* BNQ: Enet Tran Buff not Queued */
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#define ETH_TSR_COMP (1U << 5) /* COMP: Transmit Complete */
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#define ETH_TSR_UND (1U << 6) /* UND: Transmit Underrun */
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#define ETH_TSR_WR_MASK (0x67) /* write 1 to clear bits */
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/* ETH_RSR */
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#define ETH_RSR_BNA (1U << 0) /* BNA: Buffer Not Available */
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#define ETH_RSR_REC (1U << 1) /* REC: Frame Received */
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#define ETH_RSR_OVR (1U << 2) /* OVR: RX Overrun */
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/* ETH_ISR */
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#define ETH_ISR_DONE (1U << 0) /* DONE: Management Done */
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#define ETH_ISR_RCOM (1U << 1) /* RCOM: Receive Complete */
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#define ETH_ISR_RBNA (1U << 2) /* RBNA: Receive Buffer Not Avail */
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#define ETH_ISR_TOVR (1U << 3) /* TOVR: Transmit Buffer Overrun */
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#define ETH_ISR_TUND (1U << 4) /* TUND: Transmit Buffer Underrun */
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#define ETH_ISR_RTRY (1U << 5) /* RTRY: Retry Limit */
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#define ETH_ISR_TBRE (1U << 6) /* TBRE: Trasnmit Buffer Reg empty */
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#define ETH_ISR_TCOM (1U << 7) /* TCOM: Transmit Complete */
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#define ETH_ISR_TIDLE (1U << 8) /* TIDLE: Transmit Idle */
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#define ETH_ISR_LINK (1U << 9) /* LINK: Link pin delta (optional) */
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#define ETH_ISR_ROVR (1U << 10) /* ROVR: RX Overrun */
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#define ETH_ISR_ABT (1U << 11) /* ABT: Abort */
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/* ETH_MAN */
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#define ETH_MAN_BITS 0x40020000 /* HIGH and CODE bits */
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#define ETH_MAN_READ (2U << 28)
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#define ETH_MAN_WRITE (1U << 28)
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#define ETH_MAN_PHYA_BIT 23
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#define ETH_MAN_REGA_BIT 18
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#define ETH_MAN_VALUE_MASK 0xffffU
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#define ETH_MAN_REG_WR(phy, reg, val) \
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(ETH_MAN_BITS | ETH_MAN_WRITE | ((phy) << ETH_MAN_PHYA_BIT) | \
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((reg) << ETH_MAN_REGA_BIT) | ((val) & ETH_MAN_VALUE_MASK))
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#define ETH_MAN_REG_RD(phy, reg) \
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(ETH_MAN_BITS | ETH_MAN_READ | ((phy) << ETH_MAN_PHYA_BIT) | \
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((reg) << ETH_MAN_REGA_BIT))
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typedef struct {
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uint32_t addr;
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#define ETH_CPU_OWNER (1U << 0)
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#define ETH_WRAP_BIT (1U << 1)
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uint32_t status;
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#define ETH_LEN_MASK 0x7ff
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#define ETH_MAC_LOCAL_4 (1U << 23) /* Packet matched addr 4 */
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#define ETH_MAC_LOCAL_3 (1U << 24) /* Packet matched addr 3 */
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#define ETH_MAC_LOCAL_2 (1U << 25) /* Packet matched addr 2 */
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#define ETH_MAC_LOCAL_1 (1U << 26) /* Packet matched addr 1 */
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#define ETH_MAC_UNK (1U << 27) /* Unkown source address RFU */
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#define ETH_MAC_EXT (1U << 28) /* External Address */
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#define ETH_MAC_UCAST (1U << 29) /* Unicast hash match */
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#define ETH_MAC_MCAST (1U << 30) /* Multicast hash match */
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#define ETH_MAC_ONES (1U << 31) /* Global all ones bcast addr */
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} eth_rx_desc_t;
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#endif /* ARM_AT91_IF_ATEREG_H */
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