b92f01b79c
ones implemented using assembly. o) Use TRAPF_USERMODE() consistently rather than USERMODE(). Eliminate <machine/psl.h> as a result. o) Use intr_*() rather than *intr(), consistently. o) Use register_t instead of u_int in some trap code. o) Merge some more endian-related macros to machine/asm.h from NetBSD. o) Add PTR_LI macro, which loads an address with the correct sign-extension for a pointer. o) Restore interrupts when bailing out due to an excessive IRQ in nexus_setup_intr(). o) Remove unused functions from psraccess.S. o) Enter temporary virtual entries for large memory access into the page tables rather than simply hoping they stay resident in the TLB and we don't need to do a refill for them. o) Abstract out large memory mapping setup/teardown using some macros. o) Do mips_dcache_wbinv_range() when using temporary virtual addresses just like we do when we can use the direct map.
357 lines
9.2 KiB
C
357 lines
9.2 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/queue.h>
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#include <sys/smp.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <sys/timetc.h>
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#include <sys/module.h>
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#include <sys/stdint.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/systm.h>
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#include <sys/clock.h>
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#include <machine/clock.h>
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#include <machine/md_var.h>
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#include <machine/hwfunc.h>
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#include <machine/intr_machdep.h>
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#include <mips/rmi/iomap.h>
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#include <mips/rmi/clock.h>
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#include <mips/rmi/interrupt.h>
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#include <mips/rmi/pic.h>
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#include <mips/rmi/shared_structs.h>
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#ifdef XLR_PERFMON
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#include <mips/rmi/perfmon.h>
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#endif
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uint64_t counter_freq;
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uint64_t cycles_per_tick;
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uint64_t cycles_per_usec;
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uint64_t cycles_per_sec;
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uint64_t cycles_per_hz;
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u_int32_t counter_upper = 0;
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u_int32_t counter_lower_last = 0;
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#define STAT_PROF_CLOCK_SCALE_FACTOR 8
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static int scale_factor;
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static int count_scale_factor[32];
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uint64_t
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platform_get_frequency()
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{
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return XLR_PIC_HZ;
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}
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void
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mips_timer_early_init(uint64_t clock_hz)
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{
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/* Initialize clock early so that we can use DELAY sooner */
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counter_freq = clock_hz;
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cycles_per_usec = (clock_hz / (1000 * 1000));
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}
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/*
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* count_compare_clockhandler:
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*
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* Handle the clock interrupt when count becomes equal to
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* compare.
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*/
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int
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count_compare_clockhandler(struct trapframe *tf)
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{
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int cpu = PCPU_GET(cpuid);
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uint32_t cycles;
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critical_enter();
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if (cpu == 0) {
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mips_wr_compare(0);
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} else {
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count_scale_factor[cpu]++;
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cycles = mips_rd_count();
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cycles += XLR_CPU_HZ / hz;
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mips_wr_compare(cycles);
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hardclock_cpu(TRAPF_USERMODE(tf));
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if (count_scale_factor[cpu] == STAT_PROF_CLOCK_SCALE_FACTOR) {
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statclock(TRAPF_USERMODE(tf));
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if (profprocs != 0) {
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profclock(TRAPF_USERMODE(tf), tf->pc);
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}
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count_scale_factor[cpu] = 0;
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}
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/* If needed , handle count compare tick skew here */
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}
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critical_exit();
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return (FILTER_HANDLED);
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}
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unsigned long clock_tick_foo=0;
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int
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pic_hardclockhandler(struct trapframe *tf)
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{
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int cpu = PCPU_GET(cpuid);
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critical_enter();
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if (cpu == 0) {
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scale_factor++;
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clock_tick_foo++;
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/*
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if ((clock_tick_foo % 10000) == 0) {
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printf("Clock tick foo at %ld\n", clock_tick_foo);
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}
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*/
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hardclock(TRAPF_USERMODE(tf), tf->pc);
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if (scale_factor == STAT_PROF_CLOCK_SCALE_FACTOR) {
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statclock(TRAPF_USERMODE(tf));
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if (profprocs != 0) {
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profclock(TRAPF_USERMODE(tf), tf->pc);
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}
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scale_factor = 0;
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}
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#ifdef XLR_PERFMON
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if (xlr_perfmon_started)
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xlr_perfmon_clockhandler();
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#endif
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} else {
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/* If needed , handle count compare tick skew here */
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}
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critical_exit();
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return (FILTER_HANDLED);
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}
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int
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pic_timecounthandler(struct trapframe *tf)
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{
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return (FILTER_HANDLED);
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}
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void
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rmi_early_counter_init()
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{
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int cpu = PCPU_GET(cpuid);
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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/*
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* We do this to get the PIC time counter running right after system
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* start. Otherwise the DELAY() function will not be able to work
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* since it won't have a TC to read.
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*/
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xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
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xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0xffffffff & 0xffffffff));
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xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
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xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
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pic_update_control(1 << (8 + 6), 0);
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}
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void tick_init(void);
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void
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platform_initclocks(void)
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{
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int cpu = PCPU_GET(cpuid);
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void *cookie;
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/*
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* Note: Passing #3 as NULL ensures that clockhandler gets called
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* with trapframe
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*/
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/* profiling/process accounting timer interrupt for non-zero cpus */
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cpu_establish_hardintr("compare",
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(driver_filter_t *) count_compare_clockhandler,
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NULL,
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NULL,
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IRQ_TIMER,
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INTR_TYPE_CLK | INTR_FAST, &cookie);
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/* timekeeping timer interrupt for cpu 0 */
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cpu_establish_hardintr("hardclk",
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(driver_filter_t *) pic_hardclockhandler,
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NULL,
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NULL,
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PIC_TIMER_7_IRQ,
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INTR_TYPE_CLK | INTR_FAST,
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&cookie);
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/* this is used by timecounter */
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cpu_establish_hardintr("timecount",
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(driver_filter_t *) pic_timecounthandler, NULL,
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NULL, PIC_TIMER_6_IRQ, INTR_TYPE_CLK | INTR_FAST,
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&cookie);
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if (cpu == 0) {
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__uint64_t maxval = XLR_PIC_HZ / hz;
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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stathz = hz / STAT_PROF_CLOCK_SCALE_FACTOR;
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profhz = stathz;
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/* Setup PIC Interrupt */
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if (rmi_spin_mutex_safe)
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mtx_lock_spin(&xlr_pic_lock);
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xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_0, (maxval & 0xffffffff)); /* 0x100 + 7 */
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xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_1, (maxval >> 32) & 0xffffffff); /* 0x110 + 7 */
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/* 0x40 + 8 */
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/* reg 40 is lower bits 31-0 and holds CPU mask */
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xlr_write_reg(mmio, PIC_IRT_0_TIMER_7, (1 << cpu));
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/* 0x80 + 8 */
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/* Reg 80 is upper bits 63-32 and holds */
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/* Valid Edge Local IRQ */
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xlr_write_reg(mmio, PIC_IRT_1_TIMER_7, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_7_IRQ));
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pic_update_control(1 << (8 + 7), 1);
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xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
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xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0xffffffff & 0xffffffff));
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xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
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xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
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pic_update_control(1 << (8 + 6), 1);
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if (rmi_spin_mutex_safe)
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mtx_unlock_spin(&xlr_pic_lock);
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} else {
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/* Setup count-compare interrupt for vcpu[1-31] */
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mips_wr_compare((xlr_boot1_info.cpu_frequency) / hz);
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}
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tick_init();
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}
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unsigned
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__attribute__((no_instrument_function))
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platform_get_timecount(struct timecounter *tc __unused)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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return 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0);
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}
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void
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DELAY(int n)
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{
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uint32_t cur, last, delta, usecs;
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/*
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* This works by polling the timer and counting the number of
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* microseconds that go by.
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*/
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last = platform_get_timecount(NULL);
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delta = usecs = 0;
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while (n > usecs) {
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cur = platform_get_timecount(NULL);
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/* Check to see if the timer has wrapped around. */
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if (cur < last)
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delta += (cur + (cycles_per_hz - last));
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else
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delta += (cur - last);
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last = cur;
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if (delta >= cycles_per_usec) {
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usecs += delta / cycles_per_usec;
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delta %= cycles_per_usec;
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}
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}
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}
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static
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uint64_t
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read_pic_counter(void)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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uint32_t lower, upper;
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uint64_t tc;
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/*
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* Pull the value of the 64 bit counter which is stored in PIC
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* register 120+N and 130+N
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*/
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upper = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_1);
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lower = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0);
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tc = (((uint64_t) upper << 32) | (uint64_t) lower);
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return (tc);
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}
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extern struct timecounter counter_timecounter;
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void
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mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
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{
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/*
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* XXX: Do not use printf here: uart code 8250 may use DELAY so this
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* function should be called before cninit.
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*/
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counter_freq = platform_counter_freq;
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/*
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* XXX: Some MIPS32 cores update the Count register only every two
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* pipeline cycles.
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*/
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if (double_count != 0)
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counter_freq /= 2;
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cycles_per_tick = counter_freq / 1000;
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cycles_per_hz = counter_freq / hz;
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cycles_per_usec = counter_freq / (1 * 1000 * 1000);
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cycles_per_sec = counter_freq;
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counter_timecounter.tc_frequency = counter_freq;
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printf("hz=%d cyl_per_hz:%jd cyl_per_usec:%jd freq:%jd cyl_per_hz:%jd cyl_per_sec:%jd\n",
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hz,
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cycles_per_tick,
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cycles_per_usec,
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counter_freq,
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cycles_per_hz,
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cycles_per_sec
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);
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set_cputicker(read_pic_counter, counter_freq, 1);
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}
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