538 lines
15 KiB
C
538 lines
15 KiB
C
/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <net/ethernet.h>
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/haldefs.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/fmn.h>
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#include <mips/nlm/hal/pic.h>
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#include <mips/nlm/hal/sys.h>
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#include <mips/nlm/hal/nae.h>
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#include <mips/nlm/hal/uart.h>
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#include <mips/nlm/hal/poe.h>
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#include <mips/nlm/xlp.h>
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#include <mips/nlm/board.h>
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#include <mips/nlm/msgring.h>
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static uint8_t board_eeprom_buf[EEPROM_SIZE];
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static int board_eeprom_set;
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struct xlp_board_info xlp_board_info;
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struct vfbid_tbl {
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int vfbid;
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int dest_vc;
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};
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/* XXXJC : this should be derived from msg thread mask */
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static struct vfbid_tbl nlm_vfbid[] = {
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/* NULL FBID should map to cpu0 to detect NAE send msg errors */
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{127, 0}, /* NAE <-> NAE mappings */
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{51, 1019}, {50, 1018}, {49, 1017}, {48, 1016},
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{47, 1015}, {46, 1014}, {45, 1013}, {44, 1012},
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{43, 1011}, {42, 1010}, {41, 1009}, {40, 1008},
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{39, 1007}, {38, 1006}, {37, 1005}, {36, 1004},
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{35, 1003}, {34, 1002}, {33, 1001}, {32, 1000},
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/* NAE <-> CPU mappings, freeback got to vc 3 of each thread */
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{31, 127}, {30, 123}, {29, 119}, {28, 115},
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{27, 111}, {26, 107}, {25, 103}, {24, 99},
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{23, 95}, {22, 91}, {21, 87}, {20, 83},
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{19, 79}, {18, 75}, {17, 71}, {16, 67},
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{15, 63}, {14, 59}, {13, 55}, {12, 51},
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{11, 47}, {10, 43}, { 9, 39}, { 8, 35},
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{ 7, 31}, { 6, 27}, { 5, 23}, { 4, 19},
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{ 3, 15}, { 2, 11}, { 1, 7}, { 0, 3},
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};
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static struct vfbid_tbl nlm3xx_vfbid[] = {
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/* NULL FBID should map to cpu0 to detect NAE send msg errors */
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{127, 0}, /* NAE <-> NAE mappings */
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{39, 503}, {38, 502}, {37, 501}, {36, 500},
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{35, 499}, {34, 498}, {33, 497}, {32, 496},
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/* NAE <-> CPU mappings, freeback got to vc 3 of each thread */
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{31, 127}, {30, 123}, {29, 119}, {28, 115},
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{27, 111}, {26, 107}, {25, 103}, {24, 99},
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{23, 95}, {22, 91}, {21, 87}, {20, 83},
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{19, 79}, {18, 75}, {17, 71}, {16, 67},
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{15, 63}, {14, 59}, {13, 55}, {12, 51},
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{11, 47}, {10, 43}, { 9, 39}, { 8, 35},
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{ 7, 31}, { 6, 27}, { 5, 23}, { 4, 19},
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{ 3, 15}, { 2, 11}, { 1, 7}, { 0, 3},
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};
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int
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nlm_get_vfbid_mapping(int vfbid)
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{
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int i, nentries;
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struct vfbid_tbl *p;
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if (nlm_is_xlp3xx()) {
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nentries = nitems(nlm3xx_vfbid);
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p = nlm3xx_vfbid;
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} else {
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nentries = nitems(nlm_vfbid);
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p = nlm_vfbid;
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}
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for (i = 0; i < nentries; i++) {
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if (p[i].vfbid == vfbid)
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return (p[i].dest_vc);
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}
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return (-1);
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}
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int
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nlm_get_poe_distvec(int vec, uint32_t *distvec)
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{
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if (vec != 0)
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return (-1); /* we support just vec 0 */
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nlm_calc_poe_distvec(xlp_msg_thread_mask, 0, 0, 0,
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0x1 << XLPGE_RX_VC, distvec);
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return (0);
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}
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/*
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* All our knowledge of chip and board that cannot be detected by probing
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* at run-time goes here
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*/
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void
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xlpge_get_macaddr(uint8_t *macaddr)
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{
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if (board_eeprom_set == 0) {
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/* No luck, take some reasonable value */
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macaddr[0] = 0x00; macaddr[1] = 0x0f; macaddr[2] = 0x30;
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macaddr[3] = 0x20; macaddr[4] = 0x0d; macaddr[5] = 0x5b;
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} else
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memcpy(macaddr, &board_eeprom_buf[EEPROM_MACADDR_OFFSET],
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ETHER_ADDR_LEN);
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}
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static void
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nlm_setup_port_defaults(struct xlp_port_ivars *p)
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{
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p->loopback_mode = 0;
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p->num_channels = 1;
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p->free_desc_sizes = 2048;
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p->vlan_pri_en = 0;
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p->hw_parser_en = 1;
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p->ieee1588_userval = 0;
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p->ieee1588_ptpoff = 0;
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p->ieee1588_tmr1 = 0;
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p->ieee1588_tmr2 = 0;
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p->ieee1588_tmr3 = 0;
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p->ieee1588_inc_intg = 0;
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p->ieee1588_inc_den = 1;
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p->ieee1588_inc_num = 1;
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if (nlm_is_xlp3xx()) {
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p->stg2_fifo_size = XLP3XX_STG2_FIFO_SZ;
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p->eh_fifo_size = XLP3XX_EH_FIFO_SZ;
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p->frout_fifo_size = XLP3XX_FROUT_FIFO_SZ;
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p->ms_fifo_size = XLP3XX_MS_FIFO_SZ;
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p->pkt_fifo_size = XLP3XX_PKT_FIFO_SZ;
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p->pktlen_fifo_size = XLP3XX_PKTLEN_FIFO_SZ;
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p->max_stg2_offset = XLP3XX_MAX_STG2_OFFSET;
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p->max_eh_offset = XLP3XX_MAX_EH_OFFSET;
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p->max_frout_offset = XLP3XX_MAX_FREE_OUT_OFFSET;
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p->max_ms_offset = XLP3XX_MAX_MS_OFFSET;
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p->max_pmem_offset = XLP3XX_MAX_PMEM_OFFSET;
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p->stg1_2_credit = XLP3XX_STG1_2_CREDIT;
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p->stg2_eh_credit = XLP3XX_STG2_EH_CREDIT;
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p->stg2_frout_credit = XLP3XX_STG2_FROUT_CREDIT;
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p->stg2_ms_credit = XLP3XX_STG2_MS_CREDIT;
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} else {
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p->stg2_fifo_size = XLP8XX_STG2_FIFO_SZ;
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p->eh_fifo_size = XLP8XX_EH_FIFO_SZ;
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p->frout_fifo_size = XLP8XX_FROUT_FIFO_SZ;
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p->ms_fifo_size = XLP8XX_MS_FIFO_SZ;
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p->pkt_fifo_size = XLP8XX_PKT_FIFO_SZ;
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p->pktlen_fifo_size = XLP8XX_PKTLEN_FIFO_SZ;
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p->max_stg2_offset = XLP8XX_MAX_STG2_OFFSET;
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p->max_eh_offset = XLP8XX_MAX_EH_OFFSET;
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p->max_frout_offset = XLP8XX_MAX_FREE_OUT_OFFSET;
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p->max_ms_offset = XLP8XX_MAX_MS_OFFSET;
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p->max_pmem_offset = XLP8XX_MAX_PMEM_OFFSET;
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p->stg1_2_credit = XLP8XX_STG1_2_CREDIT;
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p->stg2_eh_credit = XLP8XX_STG2_EH_CREDIT;
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p->stg2_frout_credit = XLP8XX_STG2_FROUT_CREDIT;
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p->stg2_ms_credit = XLP8XX_STG2_MS_CREDIT;
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}
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switch (p->type) {
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case SGMIIC:
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p->num_free_descs = 52;
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p->iface_fifo_size = 13;
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p->rxbuf_size = 128;
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p->rx_slots_reqd = SGMII_CAL_SLOTS;
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p->tx_slots_reqd = SGMII_CAL_SLOTS;
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if (nlm_is_xlp3xx())
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p->pseq_fifo_size = 30;
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else
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p->pseq_fifo_size = 62;
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break;
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case ILC:
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p->num_free_descs = 150;
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p->rxbuf_size = 944;
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p->rx_slots_reqd = IL8_CAL_SLOTS;
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p->tx_slots_reqd = IL8_CAL_SLOTS;
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p->pseq_fifo_size = 225;
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p->iface_fifo_size = 55;
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break;
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case XAUIC:
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default:
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p->num_free_descs = 150;
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p->rxbuf_size = 944;
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p->rx_slots_reqd = XAUI_CAL_SLOTS;
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p->tx_slots_reqd = XAUI_CAL_SLOTS;
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if (nlm_is_xlp3xx()) {
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p->pseq_fifo_size = 120;
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p->iface_fifo_size = 52;
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} else {
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p->pseq_fifo_size = 225;
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p->iface_fifo_size = 55;
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}
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break;
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}
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}
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/* XLP 8XX evaluation boards have the following phy-addr
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* assignment. There are two external mdio buses in XLP --
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* bus 0 and bus 1. The management ports (16 and 17) are
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* on mdio bus 0 while blocks/complexes[0 to 3] are all
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* on mdio bus 1. The phy_addr on bus 0 (mgmt ports 16
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* and 17) match the port numbers.
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* These are the details:
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* block port phy_addr mdio_bus
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* ====================================
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* 0 0 4 1
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* 0 1 7 1
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* 0 2 6 1
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* 0 3 5 1
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* 1 0 8 1
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* 1 1 11 1
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* 1 2 10 1
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* 1 3 9 1
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* 2 0 0 1
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* 2 1 3 1
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* 2 2 2 1
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* 2 3 1 1
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* 3 0 12 1
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* 3 1 15 1
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* 3 2 14 1
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* 3 3 13 1
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*
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* 4 0 16 0
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* 4 1 17 0
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*
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* The XLP 3XX evaluation boards have the following phy-addr
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* assignments.
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* block port phy_addr mdio_bus
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* ====================================
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* 0 0 4 0
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* 0 1 7 0
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* 0 2 6 0
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* 0 3 5 0
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* 1 0 8 0
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* 1 1 11 0
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* 1 2 10 0
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* 1 3 9 0
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*/
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static void
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nlm_board_get_phyaddr(int block, int port, int *phyaddr)
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{
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switch (block) {
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case 0: switch (port) {
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case 0: *phyaddr = 4; break;
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case 1: *phyaddr = 7; break;
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case 2: *phyaddr = 6; break;
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case 3: *phyaddr = 5; break;
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}
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break;
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case 1: switch (port) {
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case 0: *phyaddr = 8; break;
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case 1: *phyaddr = 11; break;
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case 2: *phyaddr = 10; break;
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case 3: *phyaddr = 9; break;
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}
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break;
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case 2: switch (port) {
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case 0: *phyaddr = 0; break;
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case 1: *phyaddr = 3; break;
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case 2: *phyaddr = 2; break;
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case 3: *phyaddr = 1; break;
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}
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break;
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case 3: switch (port) {
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case 0: *phyaddr = 12; break;
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case 1: *phyaddr = 15; break;
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case 2: *phyaddr = 14; break;
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case 3: *phyaddr = 13; break;
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}
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break;
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case 4: switch (port) { /* management SGMII */
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case 0: *phyaddr = 16; break;
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case 1: *phyaddr = 17; break;
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}
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break;
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}
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}
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static void
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nlm_print_processor_info(void)
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{
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uint32_t procid;
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int prid, rev;
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char *chip, *revstr;
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procid = mips_rd_prid();
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prid = (procid >> 8) & 0xff;
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rev = procid & 0xff;
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switch (prid) {
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case CHIP_PROCESSOR_ID_XLP_8XX:
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chip = "XLP 832";
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break;
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case CHIP_PROCESSOR_ID_XLP_3XX:
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chip = "XLP 3xx";
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break;
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case CHIP_PROCESSOR_ID_XLP_432:
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case CHIP_PROCESSOR_ID_XLP_416:
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chip = "XLP 4xx";
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break;
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default:
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chip = "XLP ?xx";
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break;
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}
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switch (rev) {
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case 0:
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revstr = "A0"; break;
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case 1:
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revstr = "A1"; break;
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case 2:
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revstr = "A2"; break;
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case 3:
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revstr = "B0"; break;
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case 4:
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revstr = "B1"; break;
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default:
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revstr = "??"; break;
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}
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printf("Processor info:\n");
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printf(" Netlogic %s %s [%x]\n", chip, revstr, procid);
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}
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/*
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* All our knowledge of chip and board that cannot be detected by probing
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* at run-time goes here
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*/
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static int
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nlm_setup_xlp_board(int node)
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{
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struct xlp_board_info *boardp;
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struct xlp_node_info *nodep;
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struct xlp_nae_ivars *naep;
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struct xlp_block_ivars *blockp;
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struct xlp_port_ivars *portp;
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uint64_t cpldbase, nae_pcibase;
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int block, port, rv, dbtype, usecpld = 0, evp = 0, svp = 0;
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uint8_t *b;
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/* start with a clean slate */
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boardp = &xlp_board_info;
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if (boardp->nodemask == 0)
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memset(boardp, 0, sizeof(xlp_board_info));
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boardp->nodemask |= (1 << node);
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nlm_print_processor_info();
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b = board_eeprom_buf;
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rv = nlm_board_eeprom_read(node, EEPROM_I2CBUS, EEPROM_I2CADDR, 0, b,
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EEPROM_SIZE);
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if (rv == 0) {
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board_eeprom_set = 1;
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printf("Board info (EEPROM on i2c@%d at %#X):\n",
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EEPROM_I2CBUS, EEPROM_I2CADDR);
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printf(" Model: %7.7s %2.2s\n", &b[16], &b[24]);
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printf(" Serial #: %3.3s-%2.2s\n", &b[27], &b[31]);
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printf(" MAC addr: %02x:%02x:%02x:%02x:%02x:%02x\n",
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b[2], b[3], b[4], b[5], b[6], b[7]);
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} else
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printf("Board Info: Error on EEPROM read (i2c@%d %#X).\n",
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EEPROM_I2CBUS, EEPROM_I2CADDR);
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nae_pcibase = nlm_get_nae_pcibase(node);
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nodep = &boardp->nodes[node];
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naep = &nodep->nae_ivars;
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naep->node = node;
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/* frequency at which network block runs */
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naep->freq = 500;
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/* CRC16 polynomial used for flow table generation */
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naep->flow_crc_poly = 0xffff;
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naep->hw_parser_en = 1;
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naep->prepad_en = 1;
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naep->prepad_size = 3; /* size in 16 byte units */
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naep->ieee_1588_en = 1;
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naep->ilmask = 0x0; /* set this based on daughter card */
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naep->xauimask = 0x0; /* set this based on daughter card */
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naep->sgmiimask = 0x0; /* set this based on daughter card */
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naep->nblocks = nae_num_complex(nae_pcibase);
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if (strncmp(&b[16], "PCIE", 4) == 0) {
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usecpld = 0; /* XLP PCIe card */
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/* Broadcom's XLP PCIe card has the following
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* blocks fixed.
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* blk 0-XAUI, 1-XAUI, 4-SGMII(one port) */
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naep->blockmask = 0x13;
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} else if (strncmp(&b[16], "MB-EVP", 6) == 0) {
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usecpld = 1; /* XLP non-PCIe card which has CPLD */
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evp = 1;
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naep->blockmask = (1 << naep->nblocks) - 1;
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} else if ((strncmp(&b[16], "MB-S", 4) == 0) ||
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(strncmp(&b[16], "MB_S", 4) == 0)) {
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usecpld = 1; /* XLP non-PCIe card which has CPLD */
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svp = 1;
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/* 3xx chip reports one block extra which is a bug */
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naep->nblocks = naep->nblocks - 1;
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naep->blockmask = (1 << naep->nblocks) - 1;
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} else {
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printf("ERROR!!! Board type:%7s didn't match any board"
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" type we support\n", &b[16]);
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return (-1);
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}
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cpldbase = nlm_board_cpld_base(node, XLP_EVB_CPLD_CHIPSELECT);
|
|
|
|
/* pretty print network config */
|
|
printf("Network config");
|
|
if (usecpld)
|
|
printf("(from CPLD@%d):\n", XLP_EVB_CPLD_CHIPSELECT);
|
|
else
|
|
printf("(defaults):\n");
|
|
printf(" NAE@%d Blocks: ", node);
|
|
for (block = 0; block < naep->nblocks; block++) {
|
|
char *s = "???";
|
|
|
|
if ((naep->blockmask & (1 << block)) == 0)
|
|
continue;
|
|
blockp = &naep->block_ivars[block];
|
|
blockp->block = block;
|
|
if (usecpld)
|
|
dbtype = nlm_board_cpld_dboard_type(cpldbase, block);
|
|
else
|
|
dbtype = DCARD_XAUI; /* default XAUI */
|
|
|
|
/* XLP PCIe cards */
|
|
if ((!evp && !svp) && ((block == 2) || (block == 3)))
|
|
dbtype = DCARD_NOT_PRSNT;
|
|
|
|
if (block == 4) {
|
|
/* management block 4 on 8xx or XLP PCIe */
|
|
blockp->type = SGMIIC;
|
|
if (evp)
|
|
blockp->portmask = 0x3;
|
|
else
|
|
blockp->portmask = 0x1;
|
|
naep->sgmiimask |= (1 << block);
|
|
} else {
|
|
switch (dbtype) {
|
|
case DCARD_ILAKEN:
|
|
blockp->type = ILC;
|
|
blockp->portmask = 0x1;
|
|
naep->ilmask |= (1 << block);
|
|
break;
|
|
case DCARD_SGMII:
|
|
blockp->type = SGMIIC;
|
|
blockp->portmask = 0xf;
|
|
naep->sgmiimask |= (1 << block);
|
|
break;
|
|
case DCARD_XAUI:
|
|
blockp->type = XAUIC;
|
|
blockp->portmask = 0x1;
|
|
naep->xauimask |= (1 << block);
|
|
break;
|
|
default: /* DCARD_NOT_PRSNT */
|
|
blockp->type = UNKNOWN;
|
|
blockp->portmask = 0;
|
|
break;
|
|
}
|
|
}
|
|
if (blockp->type != UNKNOWN) {
|
|
for (port = 0; port < PORTS_PER_CMPLX; port++) {
|
|
if ((blockp->portmask & (1 << port)) == 0)
|
|
continue;
|
|
portp = &blockp->port_ivars[port];
|
|
nlm_board_get_phyaddr(block, port,
|
|
&portp->phy_addr);
|
|
if (svp || (block == 4))
|
|
portp->mdio_bus = 0;
|
|
else
|
|
portp->mdio_bus = 1;
|
|
portp->port = port;
|
|
portp->block = block;
|
|
portp->node = node;
|
|
portp->type = blockp->type;
|
|
nlm_setup_port_defaults(portp);
|
|
}
|
|
}
|
|
switch (blockp->type) {
|
|
case SGMIIC : s = "SGMII"; break;
|
|
case XAUIC : s = "XAUI"; break;
|
|
case ILC : s = "IL"; break;
|
|
}
|
|
printf(" [%d %s]", block, s);
|
|
}
|
|
printf("\n");
|
|
return (0);
|
|
}
|
|
|
|
int nlm_board_info_setup(void)
|
|
{
|
|
if (nlm_setup_xlp_board(0) != 0)
|
|
return (-1);
|
|
return (0);
|
|
}
|