71e7360ed9
Introduce ATA_CAM kernel option, turning ata(4) controller drivers into cam(4) interface modules. When enabled, this option deprecates all ata(4) peripheral drivers (ad, acd, ...) and interfaces and allows cam(4) drivers (ada, cd, ...) and interfaces to be natively used instead. As side effect of this, ata(4) mode setting code was completely rewritten to make controller API more strict and permit above change. While doing this, SATA revision was separated from PATA mode. It allows DMA-incapable SATA devices to operate and makes hw.ata.(ata|atapi)_dma tunable work again. Also allow ata(4) controller drivers (except some specific or broken ones) to handle larger data transfers. Previous constraint of 64K was artificial and is not really required by PCI ATA BM specification or hardware. Submitted by: nwitehorn (powerpc part)
613 lines
19 KiB
C
613 lines
19 KiB
C
/*-
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* local prototypes */
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static int ata_marvell_chipinit(device_t dev);
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static int ata_marvell_ch_attach(device_t dev);
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static int ata_marvell_setmode(device_t dev, int target, int mode);
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static int ata_marvell_edma_ch_attach(device_t dev);
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static int ata_marvell_edma_ch_detach(device_t dev);
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static int ata_marvell_edma_status(device_t dev);
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static int ata_marvell_edma_begin_transaction(struct ata_request *request);
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static int ata_marvell_edma_end_transaction(struct ata_request *request);
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static void ata_marvell_edma_reset(device_t dev);
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static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
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static void ata_marvell_edma_dmainit(device_t dev);
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/* misc defines */
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#define MV_50XX 50
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#define MV_60XX 60
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#define MV_6042 62
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#define MV_7042 72
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#define MV_61XX 61
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/*
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* Marvell chipset support functions
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*/
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#define ATA_MV_HOST_BASE(ch) \
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((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
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#define ATA_MV_EDMA_BASE(ch) \
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((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
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struct ata_marvell_response {
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u_int16_t tag;
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u_int8_t edma_status;
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u_int8_t dev_status;
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u_int32_t timestamp;
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};
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struct ata_marvell_dma_prdentry {
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u_int32_t addrlo;
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u_int32_t count;
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u_int32_t addrhi;
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u_int32_t reserved;
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};
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static int
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ata_marvell_probe(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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static struct ata_chip_id ids[] =
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{{ ATA_M88SX5040, 0, 4, MV_50XX, ATA_SA150, "88SX5040" },
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{ ATA_M88SX5041, 0, 4, MV_50XX, ATA_SA150, "88SX5041" },
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{ ATA_M88SX5080, 0, 8, MV_50XX, ATA_SA150, "88SX5080" },
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{ ATA_M88SX5081, 0, 8, MV_50XX, ATA_SA150, "88SX5081" },
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{ ATA_M88SX6041, 0, 4, MV_60XX, ATA_SA300, "88SX6041" },
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{ ATA_M88SX6042, 0, 4, MV_6042, ATA_SA300, "88SX6042" },
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{ ATA_M88SX6081, 0, 8, MV_60XX, ATA_SA300, "88SX6081" },
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{ ATA_M88SX7042, 0, 4, MV_7042, ATA_SA300, "88SX7042" },
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{ ATA_M88SX6101, 0, 0, MV_61XX, ATA_UDMA6, "88SX6101" },
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{ ATA_M88SX6102, 0, 0, MV_61XX, ATA_UDMA6, "88SX6102" },
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{ ATA_M88SX6111, 0, 1, MV_61XX, ATA_UDMA6, "88SX6111" },
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{ ATA_M88SX6121, 0, 2, MV_61XX, ATA_UDMA6, "88SX6121" },
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{ ATA_M88SX6141, 0, 4, MV_61XX, ATA_UDMA6, "88SX6141" },
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{ ATA_M88SX6145, 0, 4, MV_61XX, ATA_UDMA6, "88SX6145" },
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{ 0, 0, 0, 0, 0, 0}};
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if (pci_get_vendor(dev) != ATA_MARVELL_ID)
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return ENXIO;
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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ata_set_desc(dev);
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switch (ctlr->chip->cfg2) {
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case MV_50XX:
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case MV_60XX:
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case MV_6042:
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case MV_7042:
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ctlr->chipinit = ata_marvell_edma_chipinit;
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break;
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case MV_61XX:
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ctlr->chipinit = ata_marvell_chipinit;
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break;
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}
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ata_marvell_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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device_t child;
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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/* Create AHCI subdevice if AHCI part present. */
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if (ctlr->chip->cfg1) {
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child = device_add_child(dev, NULL, -1);
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if (child != NULL) {
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device_set_ivars(child, (void *)(intptr_t)-1);
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bus_generic_attach(dev);
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}
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}
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ctlr->ch_attach = ata_marvell_ch_attach;
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ctlr->ch_detach = ata_pci_ch_detach;
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ctlr->reset = ata_generic_reset;
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ctlr->setmode = ata_marvell_setmode;
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ctlr->channels = 1;
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return (0);
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}
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static int
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ata_marvell_ch_attach(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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int error;
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error = ata_pci_ch_attach(dev);
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/* dont use 32 bit PIO transfers */
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ch->flags |= ATA_USE_16BIT;
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ch->flags |= ATA_CHECKS_CABLE;
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return (error);
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}
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static int
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ata_marvell_setmode(device_t dev, int target, int mode)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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mode = min(mode, ctlr->chip->max_dma);
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/* Check for 80pin cable present. */
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if (mode > ATA_UDMA2 && ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x01) {
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ata_print_cable(dev, "controller");
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mode = ATA_UDMA2;
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}
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/* Nothing to do to setup mode, the controller snoop SET_FEATURE cmd. */
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return (mode);
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}
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int
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ata_marvell_edma_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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ctlr->r_type1 = SYS_RES_MEMORY;
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ctlr->r_rid1 = PCIR_BAR(0);
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if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
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&ctlr->r_rid1, RF_ACTIVE)))
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return ENXIO;
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/* mask all host controller interrupts */
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ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
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/* mask all PCI interrupts */
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ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
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ctlr->ch_attach = ata_marvell_edma_ch_attach;
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ctlr->ch_detach = ata_marvell_edma_ch_detach;
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ctlr->reset = ata_marvell_edma_reset;
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ctlr->setmode = ata_sata_setmode;
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ctlr->getrev = ata_sata_getrev;
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ctlr->channels = ctlr->chip->cfg1;
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/* clear host controller interrupts */
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ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
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if (ctlr->chip->cfg1 > 4)
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ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
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/* clear PCI interrupts */
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ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
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/* unmask PCI interrupts we want */
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ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
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/* unmask host controller interrupts we want */
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ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
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/*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
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return 0;
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}
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static int
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ata_marvell_edma_ch_attach(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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u_int64_t work;
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int i;
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ata_marvell_edma_dmainit(dev);
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work = ch->dma.work_bus;
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/* clear work area */
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bzero(ch->dma.work, 1024+256);
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bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
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BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
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/* set legacy ATA resources */
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for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
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ch->r_io[i].res = ctlr->r_res1;
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ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
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}
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ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
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ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
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ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
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ata_default_registers(dev);
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/* set SATA resources */
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switch (ctlr->chip->cfg2) {
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case MV_50XX:
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ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
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ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
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ch->r_io[ATA_SERROR].res = ctlr->r_res1;
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ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
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ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
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ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
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break;
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case MV_60XX:
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case MV_6042:
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case MV_7042:
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ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
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ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
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ch->r_io[ATA_SERROR].res = ctlr->r_res1;
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ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
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ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
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ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
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ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
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ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
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break;
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}
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ch->flags |= ATA_NO_SLAVE;
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ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
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ch->flags |= ATA_SATA;
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ata_generic_hw(dev);
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ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
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ch->hw.end_transaction = ata_marvell_edma_end_transaction;
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ch->hw.status = ata_marvell_edma_status;
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/* disable the EDMA machinery */
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ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
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DELAY(100000); /* SOS should poll for disabled */
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/* set configuration to non-queued 128b read transfers stop on error */
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ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
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/* request queue base high */
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ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
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/* request queue in ptr */
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ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
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/* request queue out ptr */
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ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
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/* response queue base high */
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work += 1024;
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ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
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/* response queue in ptr */
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ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
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/* response queue out ptr */
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ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
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/* clear SATA error register */
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ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
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/* clear any outstanding error interrupts */
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ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
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/* unmask all error interrupts */
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ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
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/* enable EDMA machinery */
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ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
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return 0;
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}
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static int
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ata_marvell_edma_ch_detach(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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if (ch->dma.work_tag && ch->dma.work_map)
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bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
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BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
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ata_dmafini(dev);
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return (0);
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}
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static int
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ata_marvell_edma_status(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
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int shift = (ch->unit << 1) + (ch->unit > 3);
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if (cause & (1 << shift)) {
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/* clear interrupt(s) */
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ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
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/* do we have any PHY events ? */
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ata_sata_phy_check_events(dev);
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}
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/* do we have any device action ? */
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return (cause & (2 << shift));
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}
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/* must be called with ATA channel locked and state_mtx held */
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static int
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ata_marvell_edma_begin_transaction(struct ata_request *request)
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{
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struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
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struct ata_channel *ch = device_get_softc(request->parent);
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u_int32_t req_in;
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u_int8_t *bytep;
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int i;
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int error, slot;
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/* only DMA R/W goes through the EMDA machine */
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if (request->u.ata.command != ATA_READ_DMA &&
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request->u.ata.command != ATA_WRITE_DMA &&
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request->u.ata.command != ATA_READ_DMA48 &&
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request->u.ata.command != ATA_WRITE_DMA48) {
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/* disable the EDMA machinery */
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if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
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ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
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return ata_begin_transaction(request);
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}
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/* check sanity, setup SG list and DMA engine */
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if ((error = ch->dma.load(request, NULL, NULL))) {
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device_printf(request->parent, "setting up DMA failed\n");
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request->result = error;
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return ATA_OP_FINISHED;
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}
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/* get next free request queue slot */
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req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
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slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
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bytep = (u_int8_t *)(ch->dma.work);
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bytep += (slot << 5);
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/* fill in this request */
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le32enc(bytep + 0 * sizeof(u_int32_t),
|
|
request->dma->sg_bus & 0xffffffff);
|
|
le32enc(bytep + 1 * sizeof(u_int32_t),
|
|
(u_int64_t)request->dma->sg_bus >> 32);
|
|
if (ctlr->chip->cfg2 != MV_6042 && ctlr->chip->cfg2 != MV_7042) {
|
|
le16enc(bytep + 4 * sizeof(u_int16_t),
|
|
(request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1));
|
|
|
|
i = 10;
|
|
bytep[i++] = (request->u.ata.count >> 8) & 0xff;
|
|
bytep[i++] = 0x10 | ATA_COUNT;
|
|
bytep[i++] = request->u.ata.count & 0xff;
|
|
bytep[i++] = 0x10 | ATA_COUNT;
|
|
|
|
bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
|
|
bytep[i++] = 0x10 | ATA_SECTOR;
|
|
bytep[i++] = request->u.ata.lba & 0xff;
|
|
bytep[i++] = 0x10 | ATA_SECTOR;
|
|
|
|
bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
|
|
bytep[i++] = 0x10 | ATA_CYL_LSB;
|
|
bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
|
|
bytep[i++] = 0x10 | ATA_CYL_LSB;
|
|
|
|
bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
|
|
bytep[i++] = 0x10 | ATA_CYL_MSB;
|
|
bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
|
|
bytep[i++] = 0x10 | ATA_CYL_MSB;
|
|
|
|
bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
|
|
bytep[i++] = 0x10 | ATA_DRIVE;
|
|
|
|
bytep[i++] = request->u.ata.command;
|
|
bytep[i++] = 0x90 | ATA_COMMAND;
|
|
} else {
|
|
le32enc(bytep + 2 * sizeof(u_int32_t),
|
|
(request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1));
|
|
|
|
i = 16;
|
|
bytep[i++] = 0;
|
|
bytep[i++] = 0;
|
|
bytep[i++] = request->u.ata.command;
|
|
bytep[i++] = request->u.ata.feature & 0xff;
|
|
|
|
bytep[i++] = request->u.ata.lba & 0xff;
|
|
bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
|
|
bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
|
|
bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0x0f);
|
|
|
|
bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
|
|
bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
|
|
bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
|
|
bytep[i++] = (request->u.ata.feature >> 8) & 0xff;
|
|
|
|
bytep[i++] = request->u.ata.count & 0xff;
|
|
bytep[i++] = (request->u.ata.count >> 8) & 0xff;
|
|
bytep[i++] = 0;
|
|
bytep[i++] = 0;
|
|
}
|
|
|
|
bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
|
|
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
|
|
|
/* enable EDMA machinery if needed */
|
|
if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
|
|
ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
|
|
while (!(ATA_INL(ctlr->r_res1,
|
|
0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
|
|
DELAY(10);
|
|
}
|
|
|
|
/* tell EDMA it has a new request */
|
|
slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
|
|
req_in &= 0xfffffc00;
|
|
req_in += (slot << 5);
|
|
ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
|
|
|
|
return ATA_OP_CONTINUES;
|
|
}
|
|
|
|
/* must be called with ATA channel locked and state_mtx held */
|
|
static int
|
|
ata_marvell_edma_end_transaction(struct ata_request *request)
|
|
{
|
|
struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
|
|
struct ata_channel *ch = device_get_softc(request->parent);
|
|
int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
|
|
u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
|
|
int res;
|
|
|
|
/* EDMA interrupt */
|
|
if ((icr & (0x0001 << (ch->unit & 3)))) {
|
|
struct ata_marvell_response *response;
|
|
u_int32_t rsp_in, rsp_out;
|
|
int slot;
|
|
|
|
/* stop timeout */
|
|
callout_stop(&request->callout);
|
|
|
|
/* get response ptr's */
|
|
rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
|
|
rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
|
|
slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
|
|
rsp_out &= 0xffffff00;
|
|
rsp_out += (slot << 3);
|
|
bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
|
|
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
|
|
response = (struct ata_marvell_response *)
|
|
(ch->dma.work + 1024 + (slot << 3));
|
|
|
|
/* record status for this request */
|
|
request->status = response->dev_status;
|
|
request->error = 0;
|
|
|
|
/* ack response */
|
|
ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
|
|
|
|
/* update progress */
|
|
if (!(request->status & ATA_S_ERROR) &&
|
|
!(request->flags & ATA_R_TIMEOUT))
|
|
request->donecount = request->bytecount;
|
|
|
|
/* unload SG list */
|
|
ch->dma.unload(request);
|
|
|
|
res = ATA_OP_FINISHED;
|
|
}
|
|
|
|
/* legacy ATA interrupt */
|
|
else {
|
|
res = ata_end_transaction(request);
|
|
}
|
|
|
|
/* ack interrupt */
|
|
ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
|
|
return res;
|
|
}
|
|
|
|
static void
|
|
ata_marvell_edma_reset(device_t dev)
|
|
{
|
|
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
|
|
/* disable the EDMA machinery */
|
|
ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
|
|
while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
|
|
DELAY(10);
|
|
|
|
/* clear SATA error register */
|
|
ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
|
|
|
|
/* clear any outstanding error interrupts */
|
|
ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
|
|
|
|
/* unmask all error interrupts */
|
|
ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
|
|
|
|
/* enable channel and test for devices */
|
|
if (ata_sata_phy_reset(dev, -1, 1))
|
|
ata_generic_reset(dev);
|
|
|
|
/* enable EDMA machinery */
|
|
ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
|
|
}
|
|
|
|
static void
|
|
ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
|
|
int error)
|
|
{
|
|
struct ata_dmasetprd_args *args = xsc;
|
|
struct ata_marvell_dma_prdentry *prd = args->dmatab;
|
|
int i;
|
|
|
|
if ((args->error = error))
|
|
return;
|
|
|
|
for (i = 0; i < nsegs; i++) {
|
|
prd[i].addrlo = htole32(segs[i].ds_addr);
|
|
prd[i].count = htole32(segs[i].ds_len);
|
|
prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
|
|
prd[i].reserved = 0;
|
|
}
|
|
prd[i - 1].count |= htole32(ATA_DMA_EOT);
|
|
KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
|
|
args->nsegs = nsegs;
|
|
}
|
|
|
|
static void
|
|
ata_marvell_edma_dmainit(device_t dev)
|
|
{
|
|
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
|
|
ata_dmainit(dev);
|
|
/* note start and stop are not used here */
|
|
ch->dma.setprd = ata_marvell_edma_dmasetprd;
|
|
|
|
/* if 64bit support present adjust max address used */
|
|
if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
|
|
ch->dma.max_address = BUS_SPACE_MAXADDR;
|
|
|
|
/* chip does not reliably do 64K DMA transfers */
|
|
if (ctlr->chip->cfg2 == MV_50XX || ctlr->chip->cfg2 == MV_60XX)
|
|
ch->dma.max_iosize = 64 * DEV_BSIZE;
|
|
}
|
|
|
|
ATA_DECLARE_DRIVER(ata_marvell);
|