81aa71755b
tree structure that encodes the level of cache sharing and other properties. - Provide several convenience functions for creating one and two level cpu trees as well as a default flat topology. The system now always has some topology. - On i386 and amd64 create a seperate level in the hierarchy for HTT and multi-core cpus. This will allow the scheduler to intelligently load balance non-uniform cores. Presently we don't detect what level of the cache hierarchy is shared at each level in the topology. - Add a mechanism for testing common topologies that have more information than the MD code is able to provide via the kern.smp.topology tunable. This should be considered a debugging tool only and not a stable api. Sponsored by: Nokia
92 lines
2.5 KiB
C
92 lines
2.5 KiB
C
/*-
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* ----------------------------------------------------------------------------
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* "THE BEER-WARE LICENSE" (Revision 42):
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* <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
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* can do whatever you want with this stuff. If we meet some day, and you think
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* this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
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* ----------------------------------------------------------------------------
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*
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* $FreeBSD$
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*
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*/
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#ifndef _MACHINE_SMP_H_
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#define _MACHINE_SMP_H_
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#ifdef _KERNEL
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#ifdef SMP
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#ifndef LOCORE
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#include <sys/bus.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <machine/apicvar.h>
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#include <machine/pcb.h>
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/* global data in mpboot.s */
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extern int bootMP_size;
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/* functions in mpboot.s */
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void bootMP(void);
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/* global data in mp_machdep.c */
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extern int mp_naps;
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extern int boot_cpu_id;
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extern struct pcb stoppcbs[];
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extern int cpu_apic_ids[];
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#ifdef COUNT_IPIS
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extern u_long *ipi_invltlb_counts[MAXCPU];
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extern u_long *ipi_invlrng_counts[MAXCPU];
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extern u_long *ipi_invlpg_counts[MAXCPU];
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extern u_long *ipi_invlcache_counts[MAXCPU];
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extern u_long *ipi_rendezvous_counts[MAXCPU];
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extern u_long *ipi_lazypmap_counts[MAXCPU];
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#endif
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/* global data in identcpu.c */
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extern int cpu_cores;
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extern int cpu_logical;
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/* IPI handlers */
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inthand_t
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IDTVEC(invltlb), /* TLB shootdowns - global */
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IDTVEC(invlpg), /* TLB shootdowns - 1 page */
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IDTVEC(invlrng), /* TLB shootdowns - page range */
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IDTVEC(invlcache), /* Write back and invalidate cache */
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IDTVEC(ipi_intr_bitmap_handler), /* Bitmap based IPIs */
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IDTVEC(cpustop), /* CPU stops & waits to be restarted */
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IDTVEC(rendezvous), /* handle CPU rendezvous */
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IDTVEC(lazypmap); /* handle lazy pmap release */
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/* functions in mp_machdep.c */
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void cpu_add(u_int apic_id, char boot_cpu);
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void cpustop_handler(void);
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void init_secondary(void);
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void ipi_selected(u_int cpus, u_int ipi);
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void ipi_all(u_int ipi);
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void ipi_all_but_self(u_int ipi);
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void ipi_self(u_int ipi);
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void ipi_bitmap_handler(struct trapframe frame);
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u_int mp_bootaddress(u_int);
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int mp_grab_cpu_hlt(void);
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void smp_cache_flush(void);
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void smp_invlpg(vm_offset_t addr);
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void smp_masked_invlpg(u_int mask, vm_offset_t addr);
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void smp_invlpg_range(vm_offset_t startva, vm_offset_t endva);
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void smp_masked_invlpg_range(u_int mask, vm_offset_t startva,
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vm_offset_t endva);
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void smp_invltlb(void);
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void smp_masked_invltlb(u_int mask);
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#ifdef STOP_NMI
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int ipi_nmi_handler(void);
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#endif
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#endif /* !LOCORE */
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#endif /* SMP */
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#endif /* _KERNEL */
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#endif /* _MACHINE_SMP_H_ */
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