bd6b2f9bef
so that code shared between imx5 and imx6 can work with OIDs under that node. Add last_reset_status (integer) and last_reset_reason (string) OIDs that provide info about the last chip reset (power-on, software reset, watchdog timeout).
63 lines
2.7 KiB
C
63 lines
2.7 KiB
C
/*-
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* Copyright (c) 2012, 2013 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Oleksandr Rybalko under sponsorship
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* from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define WDOG_CLK_FREQ 32768
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#define WDOG_CR_REG 0x00 /* Control Register */
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#define WDOG_CR_WT_MASK 0xff00 /* Count of 0.5 sec */
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#define WDOG_CR_WT_SHIFT 8
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#define WDOG_CR_WDW (1 << 7) /* Suspend WDog */
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#define WDOG_CR_WDA (1 << 5) /* Don't touch ipp_wdog */
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#define WDOG_CR_SRS (1 << 4) /* Don't touch sys_reset */
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#define WDOG_CR_WDT (1 << 3) /* Assert ipp_wdog on tout */
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#define WDOG_CR_WDE (1 << 2) /* WDog Enable */
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#define WDOG_CR_WDBG (1 << 1) /* Suspend when DBG mode */
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#define WDOG_CR_WDZST (1 << 0) /* Suspend when LP mode */
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#define WDOG_SR_REG 0x02 /* Service Register */
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#define WDOG_SR_STEP1 0x5555
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#define WDOG_SR_STEP2 0xaaaa
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#define WDOG_RSR_REG 0x04 /* Reset Status Register */
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#define WDOG_RSR_POR (1 << 4) /* Due to Power-On Reset */
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#define WDOG_RSR_TOUT (1 << 1) /* Due WDog timeout reset */
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#define WDOG_RSR_SFTW (1 << 0) /* Due Soft reset */
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#define WDOG_ICR_REG 0x06 /* Interrupt Control Register */
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#define WDOG_ICR_WIE (1 << 15) /* Enable Interrupt */
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#define WDOG_ICR_WTIS (1 << 14) /* Interrupt has occurred */
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#define WDOG_ICR_WTCT_MASK 0x00ff
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#define WDOG_ICR_WTCT_SHIFT 0 /* Interrupt hold time */
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#define WDOG_MCR_REG 0x08 /* Miscellaneous Control Register */
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#define WDOG_MCR_PDE (1 << 0)
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