4587b6e9fd
devices. This is a nop, except for what's reported by atmelbus for the resources. It would be nice if we could dymanically allocated these things, but the pmap_mapdev panics if we don't keep the static mappings, so we still need to play the carefully allocate VA space between all supported SoC game. User's with their own devices may need to make adjustments.
304 lines
9.5 KiB
C
304 lines
9.5 KiB
C
/*-
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* Copyright (c) 2009 Sylvestre Gallon. All rights reserved.
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* Copyright (c) 2010 Greg Ansley. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef AT91SAM9G20REG_H_
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#define AT91SAM9G20REG_H_
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/* Chip Specific limits */
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#define SAM9G20_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */
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#define SAM9G20_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */
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#define SAM9G20_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */
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#define SAM9G20_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */
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#define SAM9G20_PLL_A_MUL_SHIFT 16
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#define SAM9G20_PLL_A_MUL_MASK 0xFF
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#define SAM9G20_PLL_A_DIV_SHIFT 0
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#define SAM9G20_PLL_A_DIV_MASK 0xFF
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#define SAM9G20_PLL_B_MIN_IN_FREQ 2000000 /* 2 Mhz */
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#define SAM9G20_PLL_B_MAX_IN_FREQ 32000000 /* 32 Mhz */
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#define SAM9G20_PLL_B_MIN_OUT_FREQ 30000000 /* 30 Mhz */
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#define SAM9G20_PLL_B_MAX_OUT_FREQ 100000000 /* 100 Mhz */
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#define SAM9G20_PLL_B_MUL_SHIFT 16
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#define SAM9G20_PLL_B_MUL_MASK 0x3F
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#define SAM9G20_PLL_B_DIV_SHIFT 0
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#define SAM9G20_PLL_B_DIV_MASK 0xFF
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/*
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* Memory map, from datasheet :
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* 0x00000000 - 0x0ffffffff : Internal Memories
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* 0x10000000 - 0x1ffffffff : Chip Select 0
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* 0x20000000 - 0x2ffffffff : Chip Select 1
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* 0x30000000 - 0x3ffffffff : Chip Select 2
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* 0x40000000 - 0x4ffffffff : Chip Select 3
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* 0x50000000 - 0x5ffffffff : Chip Select 4
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* 0x60000000 - 0x6ffffffff : Chip Select 5
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* 0x70000000 - 0x7ffffffff : Chip Select 6
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* 0x80000000 - 0x8ffffffff : Chip Select 7
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* 0x90000000 - 0xeffffffff : Undefined (Abort)
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* 0xf0000000 - 0xfffffffff : Peripherals
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*/
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#define AT91_CHIPSELECT_0 0x10000000
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#define AT91_CHIPSELECT_1 0x20000000
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#define AT91_CHIPSELECT_2 0x30000000
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#define AT91_CHIPSELECT_3 0x40000000
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#define AT91_CHIPSELECT_4 0x50000000
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#define AT91_CHIPSELECT_5 0x60000000
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#define AT91_CHIPSELECT_6 0x70000000
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#define AT91_CHIPSELECT_7 0x80000000
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#define AT91SAM9G20_EMAC_BASE 0xffc4000
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#define AT91SAM9G20_EMAC_SIZE 0x4000
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#define AT91SAM9G20_RSTC_BASE 0xffffd00
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#define AT91SAM9G20_RSTC_SIZE 0x10
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#define RSTC_CR 0
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#define RSTC_PROCRST (1 << 0)
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#define RSTC_PERRST (1 << 2)
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#define RSTC_KEY (0xa5 << 24)
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/* USART*/
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#define AT91SAM9G20_USART_SIZE 0x4000
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#define AT91SAM9G20_USART0_BASE 0xffb0000
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#define AT91SAM9G20_USART0_PDC 0xffb0100
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#define AT91SAM9G20_USART0_SIZE AT91SAM9G20_USART_SIZE
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#define AT91SAM9G20_USART1_BASE 0xffb4000
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#define AT91SAM9G20_USART1_PDC 0xffb4100
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#define AT91SAM9G20_USART1_SIZE AT91SAM9G20_USART_SIZE
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#define AT91SAM9G20_USART2_BASE 0xffb8000
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#define AT91SAM9G20_USART2_PDC 0xffb8100
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#define AT91SAM9G20_USART2_SIZE AT91SAM9G20_USART_SIZE
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#define AT91SAM9G20_USART3_BASE 0xffd0000
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#define AT91SAM9G20_USART3_PDC 0xffd0100
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#define AT91SAM9G20_USART3_SIZE AT91SAM9G20_USART_SIZE
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#define AT91SAM9G20_USART4_BASE 0xffd4000
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#define AT91SAM9G20_USART4_PDC 0xffd4100
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#define AT91SAM9G20_USART4_SIZE AT91SAM9G20_USART_SIZE
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#define AT91SAM9G20_USART5_BASE 0xffd8000
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#define AT91SAM9G20_USART5_PDC 0xffd8100
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#define AT91SAM9G20_USART5_SIZE AT91SAM9G20_USART_SIZE
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/*TC*/
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#define AT91SAM9G20_TC0_BASE 0xffa0000
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#define AT91SAM9G20_TC0_SIZE 0x4000
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#define AT91SAM9G20_TC0C0_BASE 0xffa0000
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#define AT91SAM9G20_TC0C1_BASE 0xffa0040
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#define AT91SAM9G20_TC0C2_BASE 0xffa0080
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#define AT91SAM9G20_TC1_BASE 0xffdc000
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#define AT91SAM9G20_TC1_SIZE 0x4000
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/*SPI*/
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#define AT91SAM9G20_SPI0_BASE 0xffc8000
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#define AT91SAM9G20_SPI0_SIZE 0x4000
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#define AT91SAM9G20_IRQ_SPI0 12
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#define AT91SAM9G20_SPI1_BASE 0xffcc000
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#define AT91SAM9G20_SPI1_SIZE 0x4000
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#define AT91SAM9G20_IRQ_SPI1 13
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/* System Registers */
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#define AT91SAM9G20_SYS_BASE 0xffff000
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#define AT91SAM9G20_SYS_SIZE 0x1000
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#define AT91SAM9G20_MATRIX_BASE 0xfffee00
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#define AT91SAM9G20_MATRIX_SIZE 0x1000
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#define AT91SAM9G20_EBICSA 0x011C
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#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
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#define AT91SAM9G20_DBGU_BASE 0xffff200
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#define AT91SAM9G20_DBGU_SIZE 0x200
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/*
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* PIO
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*/
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#define AT91SAM9G20_PIOA_BASE 0xffff400
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#define AT91SAM9G20_PIOA_SIZE 0x200
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#define AT91SAM9G20_PIOB_BASE 0xffff600
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#define AT91SAM9G20_PIOB_SIZE 0x200
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#define AT91SAM9G20_PIOC_BASE 0xffff800
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#define AT91SAM9G20_PIOC_SIZE 0x200
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#define AT91RM92_PMC_BASE 0xffffc00
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#define AT91RM92_PMC_SIZE 0x100
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/* IRQs : */
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/*
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* 0: AIC
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* 1: System peripheral (System timer, RTC, DBGU)
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* 2: PIO Controller A
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* 3: PIO Controller B
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* 4: PIO Controller C
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* 5: ADC
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* 6: USART 0
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* 7: USART 1
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* 8: USART 2
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* 9: MMC Interface
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* 10: USB device port
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* 11: Two-wirte interface
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* 12: SPI 0
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* 13: SPI 1
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* 14: SSC
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* 15: - (reserved)
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* 16: - (reserved)
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* 17: Timer Counter 0
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* 18: Timer Counter 1
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* 19: Timer Counter 2
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* 20: USB Host port
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* 21: EMAC
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* 22: ISI
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* 23: USART 3
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* 24: USART 4
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* 25: USART 2
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* 26: Timer Counter 3
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* 27: Timer Counter 4
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* 28: Timer Counter 5
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* 29: AIC IRQ0
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* 30: AIC IRQ1
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* 31: AIC IRQ2
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*/
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#define AT91SAM9G20_IRQ_SYSTEM 1
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#define AT91SAM9G20_IRQ_PIOA 2
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#define AT91SAM9G20_IRQ_PIOB 3
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#define AT91SAM9G20_IRQ_PIOC 4
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#define AT91SAM9G20_IRQ_USART0 6
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#define AT91SAM9G20_IRQ_USART1 7
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#define AT91SAM9G20_IRQ_USART2 8
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#define AT91SAM9G20_IRQ_MCI 9
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#define AT91SAM9G20_IRQ_UDP 10
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#define AT91SAM9G20_IRQ_TWI 11
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#define AT91SAM9G20_IRQ_SPI0 12
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#define AT91SAM9G20_IRQ_SPI1 13
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#define AT91SAM9G20_IRQ_SSC0 14
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#define AT91SAM9G20_IRQ_SSC1 15
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#define AT91SAM9G20_IRQ_SSC2 16
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#define AT91SAM9G20_IRQ_TC0 17
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#define AT91SAM9G20_IRQ_TC1 18
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#define AT91SAM9G20_IRQ_TC2 19
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#define AT91SAM9G20_IRQ_UHP 20
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#define AT91SAM9G20_IRQ_EMAC 21
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#define AT91SAM9G20_IRQ_USART3 23
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#define AT91SAM9G20_IRQ_USART4 24
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#define AT91SAM9G20_IRQ_USART5 25
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#define AT91SAM9G20_IRQ_AICBASE 29
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/* Alias */
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#define AT91SAM9G20_IRQ_DBGU AT91SAM9G20_IRQ_SYSTEM
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#define AT91SAM9G20_IRQ_PMC AT91SAM9G20_IRQ_SYSTEM
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#define AT91SAM9G20_IRQ_WDT AT91SAM9G20_IRQ_SYSTEM
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#define AT91SAM9G20_IRQ_PIT AT91SAM9G20_IRQ_SYSTEM
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#define AT91SAM9G20_IRQ_RSTC AT91SAM9G20_IRQ_SYSTEM
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#define AT91SAM9G20_IRQ_OHCI AT91SAM9G20_IRQ_UHP
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#define AT91SAM9G20_IRQ_NAND (-1)
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#define AT91SAM9G20_AIC_BASE 0xffff000
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#define AT91SAM9G20_AIC_SIZE 0x200
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/* Timer */
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#define AT91SAM9G20_WDT_BASE 0xffffd40
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#define AT91SAM9G20_WDT_SIZE 0x10
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#define AT91SAM9G20_PIT_BASE 0xffffd30
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#define AT91SAM9G20_PIT_SIZE 0x10
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#define AT91SAM9G20_SMC_BASE 0xfffec00
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#define AT91SAM9G20_SMC_SIZE 0x200
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#define AT91SAM9G20_PMC_BASE 0xffffc00
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#define AT91SAM9G20_PMC_SIZE 0x100
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#define AT91SAM9G20_UDP_BASE 0xffa4000
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#define AT91SAM9G20_UDP_SIZE 0x4000
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#define AT91SAM9G20_MCI_BASE 0xffa8000
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#define AT91SAM9G20_MCI_SIZE 0x4000
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#define AT91SAM9G20_TWI_BASE 0xffaC000
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#define AT91SAM9G20_TWI_SIZE 0x4000
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/* XXX Needs to be carfully coordinated with
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* other * soc's so phyical and vm address
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* mapping are unique. XXX
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*/
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#define AT91SAM9G20_OHCI_VA_BASE 0xdfc00000
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#define AT91SAM9G20_OHCI_BASE 0x00500000
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#define AT91SAM9G20_OHCI_SIZE 0x00100000
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#define AT91SAM9G20_NAND_VA_BASE 0xe0000000
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#define AT91SAM9G20_NAND_BASE 0x40000000
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#define AT91SAM9G20_NAND_SIZE 0x10000000
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/* SDRAMC */
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#define AT91SAM9G20_SDRAMC_BASE 0xfffea00
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#define AT91SAM9G20_SDRAMC_MR 0x00
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#define AT91SAM9G20_SDRAMC_MR_MODE_NORMAL 0
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#define AT91SAM9G20_SDRAMC_MR_MODE_NOP 1
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#define AT91SAM9G20_SDRAMC_MR_MODE_PRECHARGE 2
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#define AT91SAM9G20_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
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#define AT91SAM9G20_SDRAMC_MR_MODE_REFRESH 4
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#define AT91SAM9G20_SDRAMC_TR 0x04
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#define AT91SAM9G20_SDRAMC_CR 0x08
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#define AT91SAM9G20_SDRAMC_CR_NC_8 0x0
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#define AT91SAM9G20_SDRAMC_CR_NC_9 0x1
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#define AT91SAM9G20_SDRAMC_CR_NC_10 0x2
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#define AT91SAM9G20_SDRAMC_CR_NC_11 0x3
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#define AT91SAM9G20_SDRAMC_CR_NC_MASK 0x00000003
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#define AT91SAM9G20_SDRAMC_CR_NR_11 0x0
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#define AT91SAM9G20_SDRAMC_CR_NR_12 0x4
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#define AT91SAM9G20_SDRAMC_CR_NR_13 0x8
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#define AT91SAM9G20_SDRAMC_CR_NR_RES 0xc
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#define AT91SAM9G20_SDRAMC_CR_NR_MASK 0x0000000c
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#define AT91SAM9G20_SDRAMC_CR_NB_2 0x00
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#define AT91SAM9G20_SDRAMC_CR_NB_4 0x10
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#define AT91SAM9G20_SDRAMC_CR_DBW_16 0x80
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#define AT91SAM9G20_SDRAMC_CR_NB_MASK 0x00000010
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#define AT91SAM9G20_SDRAMC_CR_NCAS_MASK 0x00000060
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#define AT91SAM9G20_SDRAMC_CR_TWR_MASK 0x00000780
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#define AT91SAM9G20_SDRAMC_CR_TRC_MASK 0x00007800
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#define AT91SAM9G20_SDRAMC_CR_TRP_MASK 0x00078000
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#define AT91SAM9G20_SDRAMC_CR_TRCD_MASK 0x00780000
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#define AT91SAM9G20_SDRAMC_CR_TRAS_MASK 0x07800000
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#define AT91SAM9G20_SDRAMC_CR_TXSR_MASK 0x78000000
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#define AT91SAM9G20_SDRAMC_HSR 0x0c
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#define AT91SAM9G20_SDRAMC_LPR 0x10
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#define AT91SAM9G20_SDRAMC_IER 0x14
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#define AT91SAM9G20_SDRAMC_IDR 0x18
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#define AT91SAM9G20_SDRAMC_IMR 0x1c
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#define AT91SAM9G20_SDRAMC_ISR 0x20
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#define AT91SAM9G20_SDRAMC_MDR 0x24
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#endif /* AT91SAM9G20REG_H_*/
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