73c5beec0f
multicast hash are written. There are still two distinct algorithms used, and there actually isn't any reason each driver should have its own copy of this function as they could all share one copy of it (if it grew an additional argument).
1442 lines
33 KiB
C
1442 lines
33 KiB
C
/*
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* Copyright (c) 2000 Berkeley Software Design, Inc.
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* Copyright (c) 1997, 1998, 1999, 2000
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* Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
|
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* 3. All advertising materials mentioning features or use of this software
|
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available
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* from http://www.amd.com.
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*
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* The AMD PCnet/PCI controllers are more advanced and functional
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* versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
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* backwards compatibility with the LANCE and thus can be made
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* to work with older LANCE drivers. This is in fact how the
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* PCnet/PCI chips were supported in FreeBSD originally. The trouble
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* is that the PCnet/PCI devices offer several performance enhancements
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* which can't be exploited in LANCE compatibility mode. Chief among
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* these enhancements is the ability to perform PCI DMA operations
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* using 32-bit addressing (which eliminates the need for ISA
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* bounce-buffering), and special receive buffer alignment (which
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* allows the receive handler to pass packets to the upper protocol
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* layers without copying on both the x86 and alpha platforms).
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/bpf.h>
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#include <vm/vm.h> /* for vtophys */
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#include <vm/pmap.h> /* for vtophys */
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#include <machine/bus_pio.h>
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#include <machine/bus_memio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#define PCN_USEIOSPACE
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#include <pci/if_pcnreg.h>
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MODULE_DEPEND(pcn, pci, 1, 1, 1);
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MODULE_DEPEND(pcn, ether, 1, 1, 1);
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MODULE_DEPEND(pcn, miibus, 1, 1, 1);
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|
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/* "controller miibus0" required. See GENERIC if you get errors here. */
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#include "miibus_if.h"
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|
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/*
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* Various supported device vendors/types and their names.
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*/
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static struct pcn_type pcn_devs[] = {
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{ PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
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{ PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
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{ 0, 0, NULL }
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};
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|
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static u_int32_t pcn_csr_read (struct pcn_softc *, int);
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static u_int16_t pcn_csr_read16 (struct pcn_softc *, int);
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static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int);
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static void pcn_csr_write (struct pcn_softc *, int, int);
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static u_int32_t pcn_bcr_read (struct pcn_softc *, int);
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static void pcn_bcr_write (struct pcn_softc *, int, int);
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|
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static int pcn_probe (device_t);
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static int pcn_attach (device_t);
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static int pcn_detach (device_t);
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|
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static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *);
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static int pcn_encap (struct pcn_softc *,
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struct mbuf *, u_int32_t *);
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static void pcn_rxeof (struct pcn_softc *);
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static void pcn_txeof (struct pcn_softc *);
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static void pcn_intr (void *);
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static void pcn_tick (void *);
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static void pcn_start (struct ifnet *);
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static int pcn_ioctl (struct ifnet *, u_long, caddr_t);
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static void pcn_init (void *);
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static void pcn_stop (struct pcn_softc *);
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static void pcn_watchdog (struct ifnet *);
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static void pcn_shutdown (device_t);
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static int pcn_ifmedia_upd (struct ifnet *);
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static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *);
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static int pcn_miibus_readreg (device_t, int, int);
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static int pcn_miibus_writereg (device_t, int, int, int);
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static void pcn_miibus_statchg (device_t);
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static void pcn_setfilt (struct ifnet *);
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static void pcn_setmulti (struct pcn_softc *);
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static u_int32_t pcn_mchash (caddr_t);
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static void pcn_reset (struct pcn_softc *);
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static int pcn_list_rx_init (struct pcn_softc *);
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static int pcn_list_tx_init (struct pcn_softc *);
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#ifdef PCN_USEIOSPACE
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#define PCN_RES SYS_RES_IOPORT
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#define PCN_RID PCN_PCI_LOIO
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#else
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#define PCN_RES SYS_RES_MEMORY
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#define PCN_RID PCN_PCI_LOMEM
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#endif
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static device_method_t pcn_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, pcn_probe),
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DEVMETHOD(device_attach, pcn_attach),
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DEVMETHOD(device_detach, pcn_detach),
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DEVMETHOD(device_shutdown, pcn_shutdown),
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/* bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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/* MII interface */
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DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
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DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
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DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
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{ 0, 0 }
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};
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static driver_t pcn_driver = {
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"pcn",
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pcn_methods,
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sizeof(struct pcn_softc)
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};
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static devclass_t pcn_devclass;
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DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
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DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
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#define PCN_CSR_SETBIT(sc, reg, x) \
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pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
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#define PCN_CSR_CLRBIT(sc, reg, x) \
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pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
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#define PCN_BCR_SETBIT(sc, reg, x) \
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pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
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#define PCN_BCR_CLRBIT(sc, reg, x) \
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pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
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static u_int32_t
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pcn_csr_read(sc, reg)
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struct pcn_softc *sc;
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int reg;
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{
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CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
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return(CSR_READ_4(sc, PCN_IO32_RDP));
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}
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static u_int16_t
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pcn_csr_read16(sc, reg)
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struct pcn_softc *sc;
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int reg;
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{
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CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
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return(CSR_READ_2(sc, PCN_IO16_RDP));
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}
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static void
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pcn_csr_write(sc, reg, val)
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struct pcn_softc *sc;
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int reg;
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int val;
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{
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CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
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CSR_WRITE_4(sc, PCN_IO32_RDP, val);
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return;
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}
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static u_int32_t
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pcn_bcr_read(sc, reg)
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struct pcn_softc *sc;
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int reg;
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{
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CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
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return(CSR_READ_4(sc, PCN_IO32_BDP));
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}
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static u_int16_t
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pcn_bcr_read16(sc, reg)
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struct pcn_softc *sc;
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int reg;
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{
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CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
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return(CSR_READ_2(sc, PCN_IO16_BDP));
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}
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static void
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pcn_bcr_write(sc, reg, val)
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struct pcn_softc *sc;
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int reg;
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int val;
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{
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CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
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CSR_WRITE_4(sc, PCN_IO32_BDP, val);
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return;
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}
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static int
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pcn_miibus_readreg(dev, phy, reg)
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device_t dev;
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int phy, reg;
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{
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struct pcn_softc *sc;
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int val;
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sc = device_get_softc(dev);
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if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
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return(0);
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pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
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val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
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if (val == 0xFFFF)
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return(0);
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sc->pcn_phyaddr = phy;
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return(val);
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}
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static int
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pcn_miibus_writereg(dev, phy, reg, data)
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device_t dev;
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int phy, reg, data;
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{
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struct pcn_softc *sc;
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sc = device_get_softc(dev);
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pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
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pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
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return(0);
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}
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|
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static void
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pcn_miibus_statchg(dev)
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device_t dev;
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{
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struct pcn_softc *sc;
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struct mii_data *mii;
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|
|
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sc = device_get_softc(dev);
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mii = device_get_softc(sc->pcn_miibus);
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|
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if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
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PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
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} else {
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PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
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}
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|
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return;
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}
|
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|
|
#define DC_POLY 0xEDB88320
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|
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static u_int32_t
|
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pcn_mchash(addr)
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caddr_t addr;
|
|
{
|
|
u_int32_t crc;
|
|
int idx, bit;
|
|
u_int8_t data;
|
|
|
|
/* Compute CRC for the address value. */
|
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crc = 0xFFFFFFFF; /* initial value */
|
|
|
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for (idx = 0; idx < 6; idx++) {
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for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
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crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
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}
|
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|
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return ((crc >> 26) & 0x3F);
|
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}
|
|
|
|
static void
|
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pcn_setmulti(sc)
|
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struct pcn_softc *sc;
|
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{
|
|
struct ifnet *ifp;
|
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struct ifmultiaddr *ifma;
|
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u_int32_t h, i;
|
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u_int16_t hashes[4] = { 0, 0, 0, 0 };
|
|
|
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ifp = &sc->arpcom.ac_if;
|
|
|
|
PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
|
|
|
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if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
|
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for (i = 0; i < 4; i++)
|
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pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
|
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PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
|
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return;
|
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}
|
|
|
|
/* first, zot all the existing hash bits */
|
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for (i = 0; i < 4; i++)
|
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pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
|
|
|
|
/* now program new ones */
|
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TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
|
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if (ifma->ifma_addr->sa_family != AF_LINK)
|
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continue;
|
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h = pcn_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
|
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hashes[h >> 4] |= 1 << (h & 0xF);
|
|
}
|
|
|
|
for (i = 0; i < 4; i++)
|
|
pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
|
|
|
|
PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
pcn_reset(sc)
|
|
struct pcn_softc *sc;
|
|
{
|
|
/*
|
|
* Issue a reset by reading from the RESET register.
|
|
* Note that we don't know if the chip is operating in
|
|
* 16-bit or 32-bit mode at this point, so we attempt
|
|
* to reset the chip both ways. If one fails, the other
|
|
* will succeed.
|
|
*/
|
|
CSR_READ_2(sc, PCN_IO16_RESET);
|
|
CSR_READ_4(sc, PCN_IO32_RESET);
|
|
|
|
/* Wait a little while for the chip to get its brains in order. */
|
|
DELAY(1000);
|
|
|
|
/* Select 32-bit (DWIO) mode */
|
|
CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
|
|
|
|
/* Select software style 3. */
|
|
pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Probe for an AMD chip. Check the PCI vendor and device
|
|
* IDs against our list and return a device name if we find a match.
|
|
*/
|
|
static int
|
|
pcn_probe(dev)
|
|
device_t dev;
|
|
{
|
|
struct pcn_type *t;
|
|
struct pcn_softc *sc;
|
|
int rid;
|
|
u_int32_t chip_id;
|
|
|
|
t = pcn_devs;
|
|
sc = device_get_softc(dev);
|
|
|
|
while(t->pcn_name != NULL) {
|
|
if ((pci_get_vendor(dev) == t->pcn_vid) &&
|
|
(pci_get_device(dev) == t->pcn_did)) {
|
|
/*
|
|
* Temporarily map the I/O space
|
|
* so we can read the chip ID register.
|
|
*/
|
|
rid = PCN_RID;
|
|
sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid,
|
|
0, ~0, 1, RF_ACTIVE);
|
|
if (sc->pcn_res == NULL) {
|
|
device_printf(dev,
|
|
"couldn't map ports/memory\n");
|
|
return(ENXIO);
|
|
}
|
|
sc->pcn_btag = rman_get_bustag(sc->pcn_res);
|
|
sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
|
|
mtx_init(&sc->pcn_mtx,
|
|
device_get_nameunit(dev), MTX_NETWORK_LOCK,
|
|
MTX_DEF);
|
|
PCN_LOCK(sc);
|
|
/*
|
|
* Note: we can *NOT* put the chip into
|
|
* 32-bit mode yet. The lnc driver will only
|
|
* work in 16-bit mode, and once the chip
|
|
* goes into 32-bit mode, the only way to
|
|
* get it out again is with a hardware reset.
|
|
* So if pcn_probe() is called before the
|
|
* lnc driver's probe routine, the chip will
|
|
* be locked into 32-bit operation and the lnc
|
|
* driver will be unable to attach to it.
|
|
* Note II: if the chip happens to already
|
|
* be in 32-bit mode, we still need to check
|
|
* the chip ID, but first we have to detect
|
|
* 32-bit mode using only 16-bit operations.
|
|
* The safest way to do this is to read the
|
|
* PCI subsystem ID from BCR23/24 and compare
|
|
* that with the value read from PCI config
|
|
* space.
|
|
*/
|
|
chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
|
|
chip_id <<= 16;
|
|
chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
|
|
/*
|
|
* Note III: the test for 0x10001000 is a hack to
|
|
* pacify VMware, who's pseudo-PCnet interface is
|
|
* broken. Reading the subsystem register from PCI
|
|
* config space yeilds 0x00000000 while reading the
|
|
* same value from I/O space yeilds 0x10001000. It's
|
|
* not supposed to be that way.
|
|
*/
|
|
if (chip_id == pci_read_config(dev,
|
|
PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
|
|
/* We're in 16-bit mode. */
|
|
chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
|
|
chip_id <<= 16;
|
|
chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
|
|
} else {
|
|
/* We're in 32-bit mode. */
|
|
chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
|
|
chip_id <<= 16;
|
|
chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
|
|
}
|
|
bus_release_resource(dev, PCN_RES,
|
|
PCN_RID, sc->pcn_res);
|
|
PCN_UNLOCK(sc);
|
|
mtx_destroy(&sc->pcn_mtx);
|
|
chip_id >>= 12;
|
|
sc->pcn_type = chip_id & PART_MASK;
|
|
switch(sc->pcn_type) {
|
|
case Am79C971:
|
|
case Am79C972:
|
|
case Am79C973:
|
|
case Am79C975:
|
|
case Am79C976:
|
|
case Am79C978:
|
|
break;
|
|
default:
|
|
return(ENXIO);
|
|
}
|
|
device_set_desc(dev, t->pcn_name);
|
|
return(0);
|
|
}
|
|
t++;
|
|
}
|
|
|
|
return(ENXIO);
|
|
}
|
|
|
|
/*
|
|
* Attach the interface. Allocate softc structures, do ifmedia
|
|
* setup and ethernet/BPF attach.
|
|
*/
|
|
static int
|
|
pcn_attach(dev)
|
|
device_t dev;
|
|
{
|
|
u_int32_t eaddr[2];
|
|
struct pcn_softc *sc;
|
|
struct ifnet *ifp;
|
|
int unit, error = 0, rid;
|
|
|
|
sc = device_get_softc(dev);
|
|
unit = device_get_unit(dev);
|
|
|
|
/* Initialize our mutex. */
|
|
mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
|
|
MTX_DEF | MTX_RECURSE);
|
|
#ifndef BURN_BRIDGES
|
|
/*
|
|
* Handle power management nonsense.
|
|
*/
|
|
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
|
|
u_int32_t iobase, membase, irq;
|
|
|
|
/* Save important PCI config data. */
|
|
iobase = pci_read_config(dev, PCN_PCI_LOIO, 4);
|
|
membase = pci_read_config(dev, PCN_PCI_LOMEM, 4);
|
|
irq = pci_read_config(dev, PCN_PCI_INTLINE, 4);
|
|
|
|
/* Reset the power state. */
|
|
printf("pcn%d: chip is in D%d power mode "
|
|
"-- setting to D0\n", unit,
|
|
pci_get_powerstate(dev));
|
|
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
|
|
|
|
/* Restore PCI config data. */
|
|
pci_write_config(dev, PCN_PCI_LOIO, iobase, 4);
|
|
pci_write_config(dev, PCN_PCI_LOMEM, membase, 4);
|
|
pci_write_config(dev, PCN_PCI_INTLINE, irq, 4);
|
|
}
|
|
#endif
|
|
/*
|
|
* Map control/status registers.
|
|
*/
|
|
pci_enable_busmaster(dev);
|
|
|
|
rid = PCN_RID;
|
|
sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid,
|
|
0, ~0, 1, RF_ACTIVE);
|
|
|
|
if (sc->pcn_res == NULL) {
|
|
printf("pcn%d: couldn't map ports/memory\n", unit);
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
sc->pcn_btag = rman_get_bustag(sc->pcn_res);
|
|
sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
|
|
|
|
/* Allocate interrupt */
|
|
rid = 0;
|
|
sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
|
|
RF_SHAREABLE | RF_ACTIVE);
|
|
|
|
if (sc->pcn_irq == NULL) {
|
|
printf("pcn%d: couldn't map interrupt\n", unit);
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
/* Reset the adapter. */
|
|
pcn_reset(sc);
|
|
|
|
/*
|
|
* Get station address from the EEPROM.
|
|
*/
|
|
eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
|
|
eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
|
|
bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
|
|
|
|
/*
|
|
* An AMD chip was detected. Inform the world.
|
|
*/
|
|
printf("pcn%d: Ethernet address: %6D\n", unit,
|
|
sc->arpcom.ac_enaddr, ":");
|
|
|
|
sc->pcn_unit = unit;
|
|
callout_handle_init(&sc->pcn_stat_ch);
|
|
|
|
sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
|
|
M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
|
|
|
|
if (sc->pcn_ldata == NULL) {
|
|
printf("pcn%d: no memory for list buffers!\n", unit);
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
ifp->if_softc = sc;
|
|
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
|
|
ifp->if_mtu = ETHERMTU;
|
|
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
|
|
ifp->if_ioctl = pcn_ioctl;
|
|
ifp->if_output = ether_output;
|
|
ifp->if_start = pcn_start;
|
|
ifp->if_watchdog = pcn_watchdog;
|
|
ifp->if_init = pcn_init;
|
|
ifp->if_baudrate = 10000000;
|
|
ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
|
|
|
|
/*
|
|
* Do MII setup.
|
|
*/
|
|
if (mii_phy_probe(dev, &sc->pcn_miibus,
|
|
pcn_ifmedia_upd, pcn_ifmedia_sts)) {
|
|
printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
/*
|
|
* Call MI attach routine.
|
|
*/
|
|
ether_ifattach(ifp, (u_int8_t *) eaddr);
|
|
|
|
/* Hook interrupt last to avoid having to lock softc */
|
|
error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET,
|
|
pcn_intr, sc, &sc->pcn_intrhand);
|
|
|
|
if (error) {
|
|
printf("pcn%d: couldn't set up irq\n", unit);
|
|
ether_ifdetach(ifp);
|
|
goto fail;
|
|
}
|
|
|
|
fail:
|
|
if (error)
|
|
pcn_detach(dev);
|
|
|
|
return(error);
|
|
}
|
|
|
|
/*
|
|
* Shutdown hardware and free up resources. This can be called any
|
|
* time after the mutex has been initialized. It is called in both
|
|
* the error case in attach and the normal detach case so it needs
|
|
* to be careful about only freeing resources that have actually been
|
|
* allocated.
|
|
*/
|
|
static int
|
|
pcn_detach(dev)
|
|
device_t dev;
|
|
{
|
|
struct pcn_softc *sc;
|
|
struct ifnet *ifp;
|
|
|
|
sc = device_get_softc(dev);
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
|
|
PCN_LOCK(sc);
|
|
|
|
/* These should only be active if attach succeeded */
|
|
if (device_is_attached(dev)) {
|
|
pcn_reset(sc);
|
|
pcn_stop(sc);
|
|
ether_ifdetach(ifp);
|
|
}
|
|
if (sc->pcn_miibus)
|
|
device_delete_child(dev, sc->pcn_miibus);
|
|
bus_generic_detach(dev);
|
|
|
|
if (sc->pcn_intrhand)
|
|
bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
|
|
if (sc->pcn_irq)
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
|
|
if (sc->pcn_res)
|
|
bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
|
|
|
|
if (sc->pcn_ldata) {
|
|
contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
|
|
M_DEVBUF);
|
|
}
|
|
PCN_UNLOCK(sc);
|
|
|
|
mtx_destroy(&sc->pcn_mtx);
|
|
|
|
return(0);
|
|
}
|
|
|
|
/*
|
|
* Initialize the transmit descriptors.
|
|
*/
|
|
static int
|
|
pcn_list_tx_init(sc)
|
|
struct pcn_softc *sc;
|
|
{
|
|
struct pcn_list_data *ld;
|
|
struct pcn_ring_data *cd;
|
|
int i;
|
|
|
|
cd = &sc->pcn_cdata;
|
|
ld = sc->pcn_ldata;
|
|
|
|
for (i = 0; i < PCN_TX_LIST_CNT; i++) {
|
|
cd->pcn_tx_chain[i] = NULL;
|
|
ld->pcn_tx_list[i].pcn_tbaddr = 0;
|
|
ld->pcn_tx_list[i].pcn_txctl = 0;
|
|
ld->pcn_tx_list[i].pcn_txstat = 0;
|
|
}
|
|
|
|
cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
|
|
|
|
return(0);
|
|
}
|
|
|
|
|
|
/*
|
|
* Initialize the RX descriptors and allocate mbufs for them.
|
|
*/
|
|
static int
|
|
pcn_list_rx_init(sc)
|
|
struct pcn_softc *sc;
|
|
{
|
|
struct pcn_ring_data *cd;
|
|
int i;
|
|
|
|
cd = &sc->pcn_cdata;
|
|
|
|
for (i = 0; i < PCN_RX_LIST_CNT; i++) {
|
|
if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
|
|
return(ENOBUFS);
|
|
}
|
|
|
|
cd->pcn_rx_prod = 0;
|
|
|
|
return(0);
|
|
}
|
|
|
|
/*
|
|
* Initialize an RX descriptor and attach an MBUF cluster.
|
|
*/
|
|
static int
|
|
pcn_newbuf(sc, idx, m)
|
|
struct pcn_softc *sc;
|
|
int idx;
|
|
struct mbuf *m;
|
|
{
|
|
struct mbuf *m_new = NULL;
|
|
struct pcn_rx_desc *c;
|
|
|
|
c = &sc->pcn_ldata->pcn_rx_list[idx];
|
|
|
|
if (m == NULL) {
|
|
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
|
|
if (m_new == NULL)
|
|
return(ENOBUFS);
|
|
|
|
MCLGET(m_new, M_DONTWAIT);
|
|
if (!(m_new->m_flags & M_EXT)) {
|
|
m_freem(m_new);
|
|
return(ENOBUFS);
|
|
}
|
|
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
|
|
} else {
|
|
m_new = m;
|
|
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
|
|
m_new->m_data = m_new->m_ext.ext_buf;
|
|
}
|
|
|
|
m_adj(m_new, ETHER_ALIGN);
|
|
|
|
sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
|
|
c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
|
|
c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
|
|
c->pcn_bufsz |= PCN_RXLEN_MBO;
|
|
c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
|
|
|
|
return(0);
|
|
}
|
|
|
|
/*
|
|
* A frame has been uploaded: pass the resulting mbuf chain up to
|
|
* the higher level protocols.
|
|
*/
|
|
static void
|
|
pcn_rxeof(sc)
|
|
struct pcn_softc *sc;
|
|
{
|
|
struct mbuf *m;
|
|
struct ifnet *ifp;
|
|
struct pcn_rx_desc *cur_rx;
|
|
int i;
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
i = sc->pcn_cdata.pcn_rx_prod;
|
|
|
|
while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
|
|
cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
|
|
m = sc->pcn_cdata.pcn_rx_chain[i];
|
|
sc->pcn_cdata.pcn_rx_chain[i] = NULL;
|
|
|
|
/*
|
|
* If an error occurs, update stats, clear the
|
|
* status word and leave the mbuf cluster in place:
|
|
* it should simply get re-used next time this descriptor
|
|
* comes up in the ring.
|
|
*/
|
|
if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
|
|
ifp->if_ierrors++;
|
|
pcn_newbuf(sc, i, m);
|
|
PCN_INC(i, PCN_RX_LIST_CNT);
|
|
continue;
|
|
}
|
|
|
|
if (pcn_newbuf(sc, i, NULL)) {
|
|
/* Ran out of mbufs; recycle this one. */
|
|
pcn_newbuf(sc, i, m);
|
|
ifp->if_ierrors++;
|
|
PCN_INC(i, PCN_RX_LIST_CNT);
|
|
continue;
|
|
}
|
|
|
|
PCN_INC(i, PCN_RX_LIST_CNT);
|
|
|
|
/* No errors; receive the packet. */
|
|
ifp->if_ipackets++;
|
|
m->m_len = m->m_pkthdr.len =
|
|
cur_rx->pcn_rxlen - ETHER_CRC_LEN;
|
|
m->m_pkthdr.rcvif = ifp;
|
|
|
|
(*ifp->if_input)(ifp, m);
|
|
}
|
|
|
|
sc->pcn_cdata.pcn_rx_prod = i;
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* A frame was downloaded to the chip. It's safe for us to clean up
|
|
* the list buffers.
|
|
*/
|
|
|
|
static void
|
|
pcn_txeof(sc)
|
|
struct pcn_softc *sc;
|
|
{
|
|
struct pcn_tx_desc *cur_tx = NULL;
|
|
struct ifnet *ifp;
|
|
u_int32_t idx;
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
/*
|
|
* Go through our tx list and free mbufs for those
|
|
* frames that have been transmitted.
|
|
*/
|
|
idx = sc->pcn_cdata.pcn_tx_cons;
|
|
while (idx != sc->pcn_cdata.pcn_tx_prod) {
|
|
cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
|
|
|
|
if (!PCN_OWN_TXDESC(cur_tx))
|
|
break;
|
|
|
|
if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
|
|
sc->pcn_cdata.pcn_tx_cnt--;
|
|
PCN_INC(idx, PCN_TX_LIST_CNT);
|
|
continue;
|
|
}
|
|
|
|
if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
|
|
ifp->if_oerrors++;
|
|
if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
|
|
ifp->if_collisions++;
|
|
if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
|
|
ifp->if_collisions++;
|
|
}
|
|
|
|
ifp->if_collisions +=
|
|
cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
|
|
|
|
ifp->if_opackets++;
|
|
if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
|
|
m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
|
|
sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
|
|
}
|
|
|
|
sc->pcn_cdata.pcn_tx_cnt--;
|
|
PCN_INC(idx, PCN_TX_LIST_CNT);
|
|
}
|
|
|
|
if (idx != sc->pcn_cdata.pcn_tx_cons) {
|
|
/* Some buffers have been freed. */
|
|
sc->pcn_cdata.pcn_tx_cons = idx;
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
}
|
|
ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
pcn_tick(xsc)
|
|
void *xsc;
|
|
{
|
|
struct pcn_softc *sc;
|
|
struct mii_data *mii;
|
|
struct ifnet *ifp;
|
|
|
|
sc = xsc;
|
|
ifp = &sc->arpcom.ac_if;
|
|
PCN_LOCK(sc);
|
|
|
|
mii = device_get_softc(sc->pcn_miibus);
|
|
mii_tick(mii);
|
|
|
|
/* link just died */
|
|
if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
|
|
sc->pcn_link = 0;
|
|
|
|
/* link just came up, restart */
|
|
if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
|
|
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
|
|
sc->pcn_link++;
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
pcn_start(ifp);
|
|
}
|
|
|
|
sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
|
|
|
|
PCN_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
pcn_intr(arg)
|
|
void *arg;
|
|
{
|
|
struct pcn_softc *sc;
|
|
struct ifnet *ifp;
|
|
u_int32_t status;
|
|
|
|
sc = arg;
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
/* Supress unwanted interrupts */
|
|
if (!(ifp->if_flags & IFF_UP)) {
|
|
pcn_stop(sc);
|
|
return;
|
|
}
|
|
|
|
PCN_LOCK(sc);
|
|
|
|
CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
|
|
|
|
while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
|
|
CSR_WRITE_4(sc, PCN_IO32_RDP, status);
|
|
|
|
if (status & PCN_CSR_RINT)
|
|
pcn_rxeof(sc);
|
|
|
|
if (status & PCN_CSR_TINT)
|
|
pcn_txeof(sc);
|
|
|
|
if (status & PCN_CSR_ERR) {
|
|
pcn_init(sc);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
pcn_start(ifp);
|
|
|
|
PCN_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
|
|
* pointers to the fragment pointers.
|
|
*/
|
|
static int
|
|
pcn_encap(sc, m_head, txidx)
|
|
struct pcn_softc *sc;
|
|
struct mbuf *m_head;
|
|
u_int32_t *txidx;
|
|
{
|
|
struct pcn_tx_desc *f = NULL;
|
|
struct mbuf *m;
|
|
int frag, cur, cnt = 0;
|
|
|
|
/*
|
|
* Start packing the mbufs in this chain into
|
|
* the fragment pointers. Stop when we run out
|
|
* of fragments or hit the end of the mbuf chain.
|
|
*/
|
|
m = m_head;
|
|
cur = frag = *txidx;
|
|
|
|
for (m = m_head; m != NULL; m = m->m_next) {
|
|
if (m->m_len != 0) {
|
|
if ((PCN_TX_LIST_CNT -
|
|
(sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
|
|
return(ENOBUFS);
|
|
f = &sc->pcn_ldata->pcn_tx_list[frag];
|
|
f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
|
|
f->pcn_txctl |= PCN_TXCTL_MBO;
|
|
f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
|
|
if (cnt == 0)
|
|
f->pcn_txctl |= PCN_TXCTL_STP;
|
|
else
|
|
f->pcn_txctl |= PCN_TXCTL_OWN;
|
|
cur = frag;
|
|
PCN_INC(frag, PCN_TX_LIST_CNT);
|
|
cnt++;
|
|
}
|
|
}
|
|
|
|
if (m != NULL)
|
|
return(ENOBUFS);
|
|
|
|
sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
|
|
sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
|
|
PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
|
|
sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
|
|
sc->pcn_cdata.pcn_tx_cnt += cnt;
|
|
*txidx = frag;
|
|
|
|
return(0);
|
|
}
|
|
|
|
/*
|
|
* Main transmit routine. To avoid having to do mbuf copies, we put pointers
|
|
* to the mbuf data regions directly in the transmit lists. We also save a
|
|
* copy of the pointers since the transmit list fragment pointers are
|
|
* physical addresses.
|
|
*/
|
|
static void
|
|
pcn_start(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct pcn_softc *sc;
|
|
struct mbuf *m_head = NULL;
|
|
u_int32_t idx;
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
PCN_LOCK(sc);
|
|
|
|
if (!sc->pcn_link) {
|
|
PCN_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
idx = sc->pcn_cdata.pcn_tx_prod;
|
|
|
|
if (ifp->if_flags & IFF_OACTIVE) {
|
|
PCN_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
|
|
IF_DEQUEUE(&ifp->if_snd, m_head);
|
|
if (m_head == NULL)
|
|
break;
|
|
|
|
if (pcn_encap(sc, m_head, &idx)) {
|
|
IF_PREPEND(&ifp->if_snd, m_head);
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* If there's a BPF listener, bounce a copy of this frame
|
|
* to him.
|
|
*/
|
|
BPF_MTAP(ifp, m_head);
|
|
|
|
}
|
|
|
|
/* Transmit */
|
|
sc->pcn_cdata.pcn_tx_prod = idx;
|
|
pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
|
|
|
|
/*
|
|
* Set a timeout in case the chip goes out to lunch.
|
|
*/
|
|
ifp->if_timer = 5;
|
|
|
|
PCN_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
pcn_setfilt(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct pcn_softc *sc;
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
/* If we want promiscuous mode, set the allframes bit. */
|
|
if (ifp->if_flags & IFF_PROMISC) {
|
|
PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
|
|
} else {
|
|
PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
|
|
}
|
|
|
|
/* Set the capture broadcast bit to capture broadcast frames. */
|
|
if (ifp->if_flags & IFF_BROADCAST) {
|
|
PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
|
|
} else {
|
|
PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
pcn_init(xsc)
|
|
void *xsc;
|
|
{
|
|
struct pcn_softc *sc = xsc;
|
|
struct ifnet *ifp = &sc->arpcom.ac_if;
|
|
struct mii_data *mii = NULL;
|
|
|
|
PCN_LOCK(sc);
|
|
|
|
/*
|
|
* Cancel pending I/O and free all RX/TX buffers.
|
|
*/
|
|
pcn_stop(sc);
|
|
pcn_reset(sc);
|
|
|
|
mii = device_get_softc(sc->pcn_miibus);
|
|
|
|
/* Set MAC address */
|
|
pcn_csr_write(sc, PCN_CSR_PAR0,
|
|
((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
|
|
pcn_csr_write(sc, PCN_CSR_PAR1,
|
|
((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
|
|
pcn_csr_write(sc, PCN_CSR_PAR2,
|
|
((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
|
|
|
|
/* Init circular RX list. */
|
|
if (pcn_list_rx_init(sc) == ENOBUFS) {
|
|
printf("pcn%d: initialization failed: no "
|
|
"memory for rx buffers\n", sc->pcn_unit);
|
|
pcn_stop(sc);
|
|
PCN_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Init tx descriptors.
|
|
*/
|
|
pcn_list_tx_init(sc);
|
|
|
|
/* Set up the mode register. */
|
|
pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
|
|
|
|
/* Set up RX filter. */
|
|
pcn_setfilt(ifp);
|
|
|
|
/*
|
|
* Load the multicast filter.
|
|
*/
|
|
pcn_setmulti(sc);
|
|
|
|
/*
|
|
* Load the addresses of the RX and TX lists.
|
|
*/
|
|
pcn_csr_write(sc, PCN_CSR_RXADDR0,
|
|
vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
|
|
pcn_csr_write(sc, PCN_CSR_RXADDR1,
|
|
(vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
|
|
pcn_csr_write(sc, PCN_CSR_TXADDR0,
|
|
vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
|
|
pcn_csr_write(sc, PCN_CSR_TXADDR1,
|
|
(vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
|
|
|
|
/* Set the RX and TX ring sizes. */
|
|
pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
|
|
pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
|
|
|
|
/* We're not using the initialization block. */
|
|
pcn_csr_write(sc, PCN_CSR_IAB1, 0);
|
|
|
|
/* Enable fast suspend mode. */
|
|
PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
|
|
|
|
/*
|
|
* Enable burst read and write. Also set the no underflow
|
|
* bit. This will avoid transmit underruns in certain
|
|
* conditions while still providing decent performance.
|
|
*/
|
|
PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
|
|
PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
|
|
|
|
/* Enable graceful recovery from underflow. */
|
|
PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
|
|
|
|
/* Enable auto-padding of short TX frames. */
|
|
PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
|
|
|
|
/* Disable MII autoneg (we handle this ourselves). */
|
|
PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
|
|
|
|
if (sc->pcn_type == Am79C978)
|
|
pcn_bcr_write(sc, PCN_BCR_PHYSEL,
|
|
PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
|
|
|
|
/* Enable interrupts and start the controller running. */
|
|
pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
|
|
|
|
mii_mediachg(mii);
|
|
|
|
ifp->if_flags |= IFF_RUNNING;
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
|
|
sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
|
|
PCN_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Set media options.
|
|
*/
|
|
static int
|
|
pcn_ifmedia_upd(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct pcn_softc *sc;
|
|
struct mii_data *mii;
|
|
|
|
sc = ifp->if_softc;
|
|
mii = device_get_softc(sc->pcn_miibus);
|
|
|
|
sc->pcn_link = 0;
|
|
if (mii->mii_instance) {
|
|
struct mii_softc *miisc;
|
|
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
|
|
mii_phy_reset(miisc);
|
|
}
|
|
mii_mediachg(mii);
|
|
|
|
return(0);
|
|
}
|
|
|
|
/*
|
|
* Report current media status.
|
|
*/
|
|
static void
|
|
pcn_ifmedia_sts(ifp, ifmr)
|
|
struct ifnet *ifp;
|
|
struct ifmediareq *ifmr;
|
|
{
|
|
struct pcn_softc *sc;
|
|
struct mii_data *mii;
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
mii = device_get_softc(sc->pcn_miibus);
|
|
mii_pollstat(mii);
|
|
ifmr->ifm_active = mii->mii_media_active;
|
|
ifmr->ifm_status = mii->mii_media_status;
|
|
|
|
return;
|
|
}
|
|
|
|
static int
|
|
pcn_ioctl(ifp, command, data)
|
|
struct ifnet *ifp;
|
|
u_long command;
|
|
caddr_t data;
|
|
{
|
|
struct pcn_softc *sc = ifp->if_softc;
|
|
struct ifreq *ifr = (struct ifreq *) data;
|
|
struct mii_data *mii = NULL;
|
|
int error = 0;
|
|
|
|
PCN_LOCK(sc);
|
|
|
|
switch(command) {
|
|
case SIOCSIFFLAGS:
|
|
if (ifp->if_flags & IFF_UP) {
|
|
if (ifp->if_flags & IFF_RUNNING &&
|
|
ifp->if_flags & IFF_PROMISC &&
|
|
!(sc->pcn_if_flags & IFF_PROMISC)) {
|
|
PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
|
|
PCN_EXTCTL1_SPND);
|
|
pcn_setfilt(ifp);
|
|
PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
|
|
PCN_EXTCTL1_SPND);
|
|
pcn_csr_write(sc, PCN_CSR_CSR,
|
|
PCN_CSR_INTEN|PCN_CSR_START);
|
|
} else if (ifp->if_flags & IFF_RUNNING &&
|
|
!(ifp->if_flags & IFF_PROMISC) &&
|
|
sc->pcn_if_flags & IFF_PROMISC) {
|
|
PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
|
|
PCN_EXTCTL1_SPND);
|
|
pcn_setfilt(ifp);
|
|
PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
|
|
PCN_EXTCTL1_SPND);
|
|
pcn_csr_write(sc, PCN_CSR_CSR,
|
|
PCN_CSR_INTEN|PCN_CSR_START);
|
|
} else if (!(ifp->if_flags & IFF_RUNNING))
|
|
pcn_init(sc);
|
|
} else {
|
|
if (ifp->if_flags & IFF_RUNNING)
|
|
pcn_stop(sc);
|
|
}
|
|
sc->pcn_if_flags = ifp->if_flags;
|
|
error = 0;
|
|
break;
|
|
case SIOCADDMULTI:
|
|
case SIOCDELMULTI:
|
|
pcn_setmulti(sc);
|
|
error = 0;
|
|
break;
|
|
case SIOCGIFMEDIA:
|
|
case SIOCSIFMEDIA:
|
|
mii = device_get_softc(sc->pcn_miibus);
|
|
error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
|
|
break;
|
|
default:
|
|
error = ether_ioctl(ifp, command, data);
|
|
break;
|
|
}
|
|
|
|
PCN_UNLOCK(sc);
|
|
|
|
return(error);
|
|
}
|
|
|
|
static void
|
|
pcn_watchdog(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct pcn_softc *sc;
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
PCN_LOCK(sc);
|
|
|
|
ifp->if_oerrors++;
|
|
printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
|
|
|
|
pcn_stop(sc);
|
|
pcn_reset(sc);
|
|
pcn_init(sc);
|
|
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
pcn_start(ifp);
|
|
|
|
PCN_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Stop the adapter and free any mbufs allocated to the
|
|
* RX and TX lists.
|
|
*/
|
|
static void
|
|
pcn_stop(sc)
|
|
struct pcn_softc *sc;
|
|
{
|
|
register int i;
|
|
struct ifnet *ifp;
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
PCN_LOCK(sc);
|
|
ifp->if_timer = 0;
|
|
|
|
untimeout(pcn_tick, sc, sc->pcn_stat_ch);
|
|
|
|
/* Turn off interrupts */
|
|
PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
|
|
/* Stop adapter */
|
|
PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
|
|
sc->pcn_link = 0;
|
|
|
|
/*
|
|
* Free data in the RX lists.
|
|
*/
|
|
for (i = 0; i < PCN_RX_LIST_CNT; i++) {
|
|
if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
|
|
m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
|
|
sc->pcn_cdata.pcn_rx_chain[i] = NULL;
|
|
}
|
|
}
|
|
bzero((char *)&sc->pcn_ldata->pcn_rx_list,
|
|
sizeof(sc->pcn_ldata->pcn_rx_list));
|
|
|
|
/*
|
|
* Free the TX list buffers.
|
|
*/
|
|
for (i = 0; i < PCN_TX_LIST_CNT; i++) {
|
|
if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
|
|
m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
|
|
sc->pcn_cdata.pcn_tx_chain[i] = NULL;
|
|
}
|
|
}
|
|
|
|
bzero((char *)&sc->pcn_ldata->pcn_tx_list,
|
|
sizeof(sc->pcn_ldata->pcn_tx_list));
|
|
|
|
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
|
|
PCN_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Stop all chip I/O so that the kernel's probe routines don't
|
|
* get confused by errant DMAs when rebooting.
|
|
*/
|
|
static void
|
|
pcn_shutdown(dev)
|
|
device_t dev;
|
|
{
|
|
struct pcn_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
PCN_LOCK(sc);
|
|
pcn_reset(sc);
|
|
pcn_stop(sc);
|
|
PCN_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|